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Observer xiaoqunhua
Observer
3,064 Views
Registered: ‎02-04-2017

video phy controller RX PLL selection question

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I am using the VIDEO PHY Controller core in a new design of HDMI 2.0.

My object camera solution is 1920*1440@30fps,so the TMDS clock is 1920*1440*30/10^6=82.944MHz.

Is this correct?

 

Because the NI-DRU is enabled when RX TMDS clock is below 100MHz(use CPLL) or below 61.25MHz(use QPLL)on XCKU040.

But there is no 156.25MHz DRU clock in my board,

so i want to change the RX PLL to QPLL, then there is no need DRU clock.

 

When i use a camera whose solution is 1920*1080@60fps,

My design is on with HDMI reference design in which RX PLL is CPLL.

But my design is down(TX can't work when RX is up)after changing the RX PLL to QPLL and the TX PLL to CPLL only.

Why is this coming? What can i do to make TX up?

 

Thanks

xiao

 

RX PLL&TX PLL.png
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1 Solution

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Xilinx Employee
Xilinx Employee
5,127 Views
Registered: ‎05-07-2015

Re: video phy controller RX PLL selection question

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HI @xiaoqunhua


1920*1440@60fpos is a valid CEA format  (30 fps format is not listed in CEA timing tables which we use).
Are you registering this customer resolution? (AR68227)


Also for pixel clock calculation , you have to use HTOTAL*VTOTAL*framerate , not the HACTIVE *VACTIVE*frame rate.
Hence calculate the pixel clock frequency   for the input resolution correctly . and check whether it falls in the supported range QPLL0 or QPLL1  (refer page 52 ,53 of PG230  vid phy guide). and then  choose the appropriate QPLL.



Thanks
Bharath
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5 Replies
Explorer
Explorer
3,038 Views
Registered: ‎08-14-2007

Re: video phy controller RX PLL selection question

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Firstly 1920*1440@30fps isn't a standard Video format defined in CEA-861-F spec.

When TX uses CPLL, the TMDS clock frequency is below the supported range, it uses oversampling to make reference clock frequency falls into the supported range. The oversampling factor can only be 3 or 5

 

Observer xiaoqunhua
Observer
3,015 Views
Registered: ‎02-04-2017

Re: video phy controller RX PLL selection question

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My input solution is 1920*1440@30fps,but output solution is 3840*2160@30fps.

So TX PLL isn't a problem, if i can solve NI-DRU problem.

Can i change the RX PLL to QPLL and the TX PLL to CPLL to do this?

 

Thanks

xiao

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Explorer
Explorer
2,986 Views
Registered: ‎08-14-2007

Re: video phy controller RX PLL selection question

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I can't see any reason that prevents you using QPLL as RX PLL and CPLL as TX PLL. Since v2016.3, you can generate HDMI example design by using "Open IP Example Design". I don't know why you use TX-QPLL RX-CPLL settings to generate example design. If you want to use CPLL at TX side, it's better to start with the example which has the right settings.

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Xilinx Employee
Xilinx Employee
5,128 Views
Registered: ‎05-07-2015

Re: video phy controller RX PLL selection question

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HI @xiaoqunhua


1920*1440@60fpos is a valid CEA format  (30 fps format is not listed in CEA timing tables which we use).
Are you registering this customer resolution? (AR68227)


Also for pixel clock calculation , you have to use HTOTAL*VTOTAL*framerate , not the HACTIVE *VACTIVE*frame rate.
Hence calculate the pixel clock frequency   for the input resolution correctly . and check whether it falls in the supported range QPLL0 or QPLL1  (refer page 52 ,53 of PG230  vid phy guide). and then  choose the appropriate QPLL.



Thanks
Bharath
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Adventurer
Adventurer
2,729 Views
Registered: ‎02-04-2017

Re: video phy controller RX PLL selection question

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now  HDMI change rx's cpll to QPLL and tx's qpll to cpll, rx is up, but tx is not up, SDK can auto adjust it for QPLL and CPLL?

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