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Adventurer
Adventurer
12,051 Views
Registered: ‎08-24-2008

BRAM power consumption in Virtex 4

Hi,

 

I have a design , D1, that uses a BRAM. I analyzed the design's power for a set of inputs using Xpower Analyzer and the post place and route simulation model with SAIF file generated by ISim. The BRAM power consumption is shown to be "Y mW".

 

Now, I did a separate design, D2, with just the exact same BRAM and exactly the same read sequence as in D1. This time Xpower Analyzer gave "Z mW". The same read addresses were used and the same data was present in BRAM in D2 as in D1. D2 had no other logic. Just reading data from a preloaded BRAM.

 

The only difference between the BRAM in D1 and in D2 is that in D1, the BRAM enable signal is high only for around 47% of the total simulation time while in D2 it is always high. However, the BRAM enable in D1 is high only as long as the read takes place which is exactly similar to as in D2. There is no writing to BRAM in either D1 or D2.

 

To my surprise, Z > Y. 

 

Can anyone explain this? I figured out that XPA uses BRAM enable toggle rate as a factor in power computation and clearly this toggle rate is different in the two designs based on the way XPA calculates toggle rate and it influences power value.

 

Would it not be more appropriate to compare energy numbers and not power numbers for BRAM in the two designs? I guess the energy numbers should be the same in both the cases. And would it not be better for XPA to improve its power calculation methodology because clearly results like that above can be misleading or better still report energy values as well?

 

Any comments?

 

 

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6 Replies
Xilinx Employee
Xilinx Employee
12,037 Views
Registered: ‎01-03-2008

Re: BRAM power consumption in Virtex 4

Your message is a bit convoluted, but here is what I read


D1 with BRAM with read enable 47% = Y mW

D2 with BRAM with read enable 100% = Z mW

 

Z > Y

 

This is exactly what I would expect to see in a system.  Disabling the BlockRAM will always save power.

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Adventurer
Adventurer
12,020 Views
Registered: ‎08-24-2008

Re: BRAM power consumption in Virtex 4

I agree that disabling BRAM would save system power. Those numbers were referring to the "power consumption of BRAM " reported by XPA. It is the same sequence of operations performed on BRAM in both D1 and D2, however their power values are different. I was a bit intrigued by that as based on intuition for the same set and kind of operations on a BRAM, its power values should be same.

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Xilinx Employee
Xilinx Employee
12,013 Views
Registered: ‎01-03-2008

Re: BRAM power consumption in Virtex 4

> for the same set and kind of operations on a BRAM, its power values should be same.

 

But the operation is not the same for the two designs.  In one case the BRAM is only read/active 47% of the time.

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Adventurer
Adventurer
12,001 Views
Registered: ‎08-24-2008

Re: BRAM power consumption in Virtex 4

I get your point about the BRAM being active for different amounts of time in the two designs.

 

I did following experiments for D2:

 

a) I ran the post place and route timing simulation for 280 ns. Then XPA reported 2.54 mW as BRAM's power consumption.

(the BRAM enable signal was tied high)

 

b) This time I brought BRAM enabIe signal to the top so that I may control it through testbench.  I  reran the post place and route timing simulation for 280 ns and disable BRAM enable signal at 250 ns. Then XPA reported 1.36 mW as BRAM's power consumption and enable rate as 53.57%.

 

XPA reported signal rate of 22.7% in both (a) and (b). Except for the 30 ns duration when BRAM enable went low in (b), there is no difference between (a) and (b) in terms of functionality.

 

Would that 30 ns make so much difference as to reduce power by nearly 50%? Intuitively, for both (a) and (b), power values should be close, shouldn't that be the case? Which formula does XPA use to calculate the power value?

 

I also noticed one more thing. When I simulated (b) for 1000 ns (all things remaining same as for 280 ns), the clock power did not change. XPA reported clock power as 8.56 mW in both the cases.
 Shouldn't the clock power values change?

 

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Xilinx Employee
Xilinx Employee
11,997 Views
Registered: ‎01-03-2008

Re: BRAM power consumption in Virtex 4

> Would that 30 ns make so much difference as to reduce power by nearly 50%?

The real factor is the 53.57% enable rate, not the 30ns.  1.36mW/2.54mW = 53.54%

 

> Intuitively, for both (a) and (b), power values should be close, shouldn't that be the case?

No it isn't as I have said several times.   In one case you have the BRAM used 100% of the time and in the other 53% that is a vastly different workload.

 

> Shouldn't the clock power values change?

There is nothing in your designs that has make any change to the clock network, so the power is the same.

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Adventurer
Adventurer
11,991 Views
Registered: ‎08-24-2008

Re: BRAM power consumption in Virtex 4

> Would that 30 ns make so much difference as to reduce power by nearly 50%?

>The real factor is the 53.57% enable rate, not the 30ns.  1.36mW/2.54mW = 53.54%

 

> Intuitively, for both (a) and (b), power values should be close, shouldn't that be the case?

>No it isn't as I have said several times.   In one case you have the BRAM used 100% of the time and in the other 53% that is a vastly different workload.

 

 

I would agree for the time being with your argument. But to me it appears like this argument is based purely on numbers like 100% and 53%. There is no different workload except for those 30 ns when BRAM is not enabled. May be I need to measure it on board to see how it is to be sure that it is not an issue with how XPA calculates these values but an issue with my understanding.

 

> Shouldn't the clock power values change?

>There is nothing in your designs that has make any change to the clock network, so the power is the same.

 

So, that means that the clock network can keep switching forever but if there is no switching activity associated with the logic implemented on FPGA (even after an initial period of activity) , the clock power will remain constant. So, the clock network will dissipate energy at a constant rate. That is something interesting!

 

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