07-14-2011 02:13 AM
I am new in FPGA.....
I configured a Block RAM (depth 256, width 72)
The size should be 18K
but the resources used is one 36K Block RAM....
what is the problem??
07-14-2011 06:35 AM
<36K uses all of one 36K Block RAM.
Not necessarily true. For V5 you can split a 36K BRAM into two 18K BRAMs. However I believe the
72-bit width is causing the issue. There are only a limited number of connections for each BRAM
so when you use all of the data lines, then you lose the other 18Kb half of the BRAM because there's
no remaining connections for data. Look at the v5 User Guide where the rules are explained. An 18K
BRAM with a single port can be wider than a DUAL port 18K BRAM, for example.
07-14-2011 08:09 PM
You are right. I checked the document and the max data width should be 36.
Just want to ask.
If I keep the depth 256 (8 bit addr) and create more Block RAM,
for example, 2 BRAM (256 depth and 36 width)
will xilinx use the same 18K BRAM??
or the remind parts of 18K BRAM are wasted and use 2 18K BRAM??
Thanks for answering my question.
07-14-2011 08:26 PM
It's cheap and easy in ISE to try out all sorts of configurations. Take your idea for a spin!
Do you think if you run two 36-bit wide BRAMs in parallel, you might achieve something similar to a single 72-bit wide BRAM?
-- Bob Elkind