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Visitor
Visitor
3,194 Views
Registered: ‎08-02-2010

Can ISE "just do the right thing" with IDELAYCTRLs?

I have an SOC design with a number of cores from different sources (e.g. Coregen, outside vendors, in-house designs), and several of them have IODELAYE1 blocks.  The design is constantly evolving, and we have several variation on it.  Frequently, when I add or remove a core, or even  when the tools produce a change in placement, I have to resolve errors related to having too many or too few, or over- or under-constrained IDELAYCTRLs. 

 

Is there a way to tell ISE to just instantiate and associate IDELAYCTRLs in some reasonable default way, and then I can come back and tweak it if and when I need to?

 

Thanks,

Eric

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Xilinx Employee
Xilinx Employee
3,150 Views
Registered: ‎11-28-2007

Yes, use "IODELAY_GROUP" constraint. Check the constraint UG below for more details on the constraint (By the way, download Xilinx Document Navigator to manage all Xilinx documents) :

 

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/cgd.pdf

 


@andersoe wrote:

I have an SOC design with a number of cores from different sources (e.g. Coregen, outside vendors, in-house designs), and several of them have IODELAYE1 blocks.  The design is constantly evolving, and we have several variation on it.  Frequently, when I add or remove a core, or even  when the tools produce a change in placement, I have to resolve errors related to having too many or too few, or over- or under-constrained IDELAYCTRLs. 

 

Is there a way to tell ISE to just instantiate and associate IDELAYCTRLs in some reasonable default way, and then I can come back and tweak it if and when I need to?

 

Thanks,

Eric




Cheers,
Jim
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