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Observer aobeid
Observer
7,678 Views
Registered: ‎09-25-2012

Clocking from a Neighboring GTP/GTX_DUAL Tile

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Hi,

 

I've recently been working on sharing the differential clock between two GTX tiles.

 

Brief description:


FPGA: Virtex-5 XC5VFX70T FFG665

Using Aurora Core for transmission.

Targeted tiles: MGT118, MGT116.

Goal: Workaround for PCB deficiency where one tile has the differential clock pins connected and another tile has the RocketIO connected.


 

According to UG353 Chapter 7, clocking from a neighboring GTP/GTX_DUAL tile is possible under certain conditions where the number of tiles between the sourcing tile and the target tile shouldn't exceed three.

 

Using the Core Generator wizard, I've generated the corresponding design. However, I get the following error during the Mapping step:


ERROR:PhysDesignRules:2270 - Block

Modul_aurora_example_design/aurora_module_i/gtx_wrapper_i/GTX_TILE_INST_LANE1
/gtx_tile_i (GTX_DUAL_X0Y5) needs GTX_DUAL_X0Y4 instantiated: When using a
GTP/GTX with a REFCLK coming from an IBUFDS element near another GTP/GTX and
forwarding that clock using dedicated routing, each GTP in between the source
and destination must be instantiated in the correct manner (See AR 33473). If
you don't instantiate these other GTP tiles the software tools will route the
REFCLK correctly, but the design may not work in hardware.
ERROR:PhysDesignRules:2270 - Block
Modul_aurora_example_design/aurora_module_i/gtx_wrapper_i/GTX_TILE_INST_LANE1
/gtx_tile_i (GTX_DUAL_X0Y5) needs GTX_DUAL_X0Y3 instantiated: When using a
GTP/GTX with a REFCLK coming from an IBUFDS element near another GTP/GTX and
forwarding that clock using dedicated routing, each GTP in between the source
and destination must be instantiated in the correct manner (See AR 33473). If
you don't instantiate these other GTP tiles the software tools will route the
REFCLK correctly, but the design may not work in hardware.
ERROR:Pack:1642 - Errors in physical DRC.


 

Note worthy, that I've been able to successfully generate, synthesize and download the same design using different tiles combination, MGT118 and MGT114 (Verified using ChipScope).

In what follows is the UCF additional information concerning tile matches from the example design:

# X0Y0 -> Tile #126 on Board
# X0Y1 -> Tile #122 on Board
# X0Y2 -> Tile #118 on Board
# X0Y3 -> Tile #114 on Board
# X0Y4 -> Tile #112 on Board
# X0Y5 -> Tile #116 on Board
# X0Y6 -> Tile #120 on Board
# X0Y7 -> Tile #124 on Board

 

I've also read the (AR 33473), which propose a instantiation fix that shouldn't be this case since another tile pair is working and only difference is the tile pair selection in the Core Generator wizard.

 

Questions:

- How is the GTX tile numbering works? Is it based on the MGT{X} number or the GTX_DUAL_X0Y{X} number?

- Why did the MGT118/MGT114 work and the MGT118/116 gave an error?

 

Please help me understand this case.

 

Thanks in advance for your help and cooperation.

 

 

Best Regards

Ahmad Obeid

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1 Solution

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Xilinx Employee
Xilinx Employee
8,814 Views
Registered: ‎01-03-2008

Re: Clocking from a Neighboring GTP/GTX_DUAL Tile

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> - Why did the MGT118/MGT114 work and the MGT118/116 gave an error?

 

In the table that you provided MGT118 is in location X0Y2 and MGT114 is in location X0Y3 which is adjacent and it works. While MGT116 is in location X0Y5 which is not adjacent to X0Y2 which is why it doesn't work.

------Have you tried typing your question into Google? If not you should before posting.
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Xilinx Employee
Xilinx Employee
8,815 Views
Registered: ‎01-03-2008

Re: Clocking from a Neighboring GTP/GTX_DUAL Tile

Jump to solution

> - Why did the MGT118/MGT114 work and the MGT118/116 gave an error?

 

In the table that you provided MGT118 is in location X0Y2 and MGT114 is in location X0Y3 which is adjacent and it works. While MGT116 is in location X0Y5 which is not adjacent to X0Y2 which is why it doesn't work.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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