07-14-2011 11:30 PM
DCM reset circuit design on virtex5:
How many cycles (How long) should we wait once a reset of 3 cycles long is assserted after an unlock has been detected to check whether the DCM is locked or not?
07-15-2011 02:39 AM
07-15-2011 03:43 AM
the question is: After a reset, how long does it take for a DCM to get locked under normal conditions.
giving another reset too soon will prevent DCM from getting locked. settling time for a DCM is what I wonder.
07-15-2011 07:34 AM
Lock time is specified in the Virtex 5 data sheet (ds202) under the very enlightening title of
"Miscellaneous Timing Parameters." The maximum lock time depends on the frequency
of the input clock, and also whether you're using the FX outputs or the DLL outputs. In no
case is it more than 5 ms for DLL or 10 ms for FX outputs.
Then to throw a monkey-wrench into the works, they add:
Multiplier factor for DLL Lock time with Fine Shift: 2.0
So if you use the "fine" shift feature of the DLL you could double the lock time.
It is reasonable to assume that these lock times are dependent on the input clock being
stable during the entire locking period.
Another word of caution on DCM's:
DCM outputs DO NOT TOGGLE while you assert reset! DON'T USE THE DCM'S OUTPUTS
TO CLOCK THE RESET LOGIC!
10-11-2011 09:28 PM - edited 10-11-2011 11:02 PM
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