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Contributor
Contributor
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Registered: ‎08-22-2007

Dualport ROM

I have a made a VHDL module for a dualport ram which I have used in several projects over the years and it works amyzingly well. I am now trying to convert this to a ROM but I get some errors:

 

I have used a shared variable and two process for my RAM but if I remove the write-ports I get: ERROR:Xst:2073 - Unexpected use of shared variable <ram>

 

I then change my shared variable to a regular signal and everything works fine except that it occupies twice as many BRAM cells. A dual-port ram with a shared variable takes 18 blocks but when I change it to a signal and remove the write ports, it consumes 36 blocks. Does anyone have a clue on this?

 

Regards

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Professor
Professor
5,461 Views
Registered: ‎08-14-2007

It's not clear why XST cannot infer dual-port memory without a write port, but for a workaround

you could leave  the write port in the code, i.e. use the same dual-port RAM code you have now,

and just tie off the unused signals when you instantiate the RAM.

-- Gabor
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Visitor
Visitor
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Registered: ‎03-29-2010

ERROR Xst:2073 - Unexpected use of shared variable <conjunto_reg>.

I have the same problem, but only with spartan3a, xc3s700an... when I change the device the problem does not appear.

 

 

 I am looking for the solution. Please if you have an Idea tell me... maybe together we can find a solution.

 

I tried using the language templates suggestions, but it does not work.

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Registered: ‎08-19-2015

Five years later...

 

I came across a similar problem in Vivado 2015.2.

 

module DPROM(Clk,EN,A1,Q1,A2,Q2);

input Clk, EN;
input [11:0] A1, A2;
output reg [7:0] Q1=0, Q2=0;

reg [7:0] T[0:4095];
integer i;
initial for (i=0; i<4096; i=i+1) T[i] = (i * (i + 2)) ^ 8'h55; // it is unimportant what is written here always @(posedge Clk) if (EN) {Q1, Q2} <= {T[A1], T[A2]}; endmodule

In this example everything is ok: synthesis gives one RAMB36. But if initial values of output registers aren't equal among themselves synthesis gives two RAMB36s.

 

output reg [7:0] Q1=0, Q2=5;

In ISE14.x it works correctly.

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