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4,359 Views
Registered: ‎09-14-2009

ERROR:Pack:1653

Hi all,

 

This is the Error I get in ESE:

------------------------------------------------------

Running delay-based LUT packing...
ERROR:Pack:1653 - At least one timing constraint is impossible to meet because
   component delays alone exceed the constraint. A timing constraint summary
   below shows the failing constraints (preceded with an Asterisk (*)). Please
   use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and
   PCF files to identify which constraints and paths are failing because of the
   component delays alone. If the failing path(s) is mapped to Xilinx components
   as expected, consider relaxing the constraint. If it is not mapped to
   components as expected, re-evaluate your HDL and how synthesis is optimizing
   the path. To allow the tools to bypass this error, set the environment
   variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.
   For more information about the Timing Analyzer, consult the Xilinx Timing
   Analyzer Reference manual; for more information on TRCE, consult the Xilinx
   Development System Reference Guide "TRACE" chapter.
Mapping completed.
See MAP report file "system_map.mrp" for details.
Problem encountered during the packing phase.
Design Summary
--------------
Number of errors   :   1
Number of warnings :  49
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
make: *** [__xps/system_routed] Error 1
Done!

------------------------------------------------------ 

 

I did read in the homepage of Xilinx that the problem was solved in the EDK updae 10.1.03, which I installed.

But I get the same problem.

Can somebody help me? Please.

 

Regards

/Arthur 

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2 Replies
robinliuy
Voyager
Voyager
4,333 Views
Registered: ‎05-21-2008

Hi,

I think you can try this environment viriable.

SET XIL_TIMING_ALLOW_IMPOSSIBLE=1

 

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4,316 Views
Registered: ‎09-14-2009

Thanks!

 

Regards

/Arthur 

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