01-07-2014 01:42 PM
Need to generate a low speed single-ended clock to test a very slow serdes channel (long story of why it's so low and single ended). I'm trying to use the V5 DCM in low frequency mode to accept an input clock of 2.5MHz and generate 15MHz-17.5MHz. When I use the GUI Core Generator and in selecting Maximum Range performance mode I can only choose a minimum of 19MHz for the input clock.
Here are my clock sources
Board input clock of 32MHz and 120MHz.
So I planned on divided down the 32MHz by 12 to get 2.666MHz (my shift clock), or divide down the 120MHz to 7.5MHz, and then further divide the 7.5MHz with a counter to get 2.5MHz. I would like to send this 2.666MHz to a DCM and multiply up by 6 to get 16MHz.
Is this possible? Do I have to manually configure the DCM?
01-07-2014 02:08 PM
You can use the DCM_ADV in Virtex 5 for low frequency applied to DFS outputs as follows:
1) Select your input clock frequency
2) Check only CLKFX
3) Select "None" for Feedback Source
4) On the third page select the Output Frequency
01-08-2014 09:20 AM
As explained in the Clock Management section in UG190:
The DCM contains a delay-locked loop (DLL) to eliminate clock distribution delays, by deskewing the DCM's output clocks with respect to the input clock. Unfortunately, for the frequencies you require you cannot use the DLL output clocks.
When the CLKFB pin is not connected, DCM clock outputs are not deskewed to CLKIN. However, the relative phase relationship between all output clocks is preserved.