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Adventurer
Adventurer
4,507 Views
Registered: ‎12-01-2010

How could I get LUT-level netlist in Xilinx ISE?

 

Hi, friends,

 

I need to convert the high level design to LUT level netlist, and then make corrections to it.

In a paper, author says:

"The translate step generates a Verilog netlist that can easily be parsed. This netlist consists out of declarations of primitive modules of the device"

The netlist is shown as following:

******************************************
...
defparam LUT_37.INIT = 16'hC800;
X_LUT4 LUT37 (.ADR0(n7), .ADR1(n4), .ADR2(n3), .ADR3(n8), .o(n41);
....

******************************************
I searched all the files in the project folder, but didn't find this kind of netlist.

I just want to know how to get this kind of netlist in Xilinx FPGA?

Thanks very much!!

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3 Replies
Scholar austin
Scholar
4,504 Views
Registered: ‎02-27-2008

Re: How could I get LUT-level netlist in Xilinx ISE?

b,

You may output a EDIF netlist of the design, or you may output the .xdl netlist (internal Xilinx proprietary representation) of the design.

Either of these will show the actual elements used: LUT, DFF, singles, doubles, quads (wires) etc.

You may also examine the primitives in FPGA_Editor.

Why do you wish to do this?

What is it you are trying to do (learn)?

Why would your design need to be "corrected" at the LUT level?

Austin Lesea
Principal Engineer
Xilinx San Jose
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Newbie evgeni
Newbie
4,495 Views
Registered: ‎06-02-2011

Re: How could I get LUT-level netlist in Xilinx ISE?

 

Hi,
 
What you describe looks like simulation netlist. You can generate it using Xilinx netgen tool either in command-line mode or from the ISE (generate post-{translate,map,par} simulation model).
Thanks,

 

Tags (1)
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Adventurer
Adventurer
4,482 Views
Registered: ‎12-01-2010

Re: How could I get LUT-level netlist in Xilinx ISE?

b,

>You may output a EDIF netlist of the design, or you may output the .xdl netlist (internal Xilinx proprietary representation) >of the design.
 
Hi, thanks for your rely.
  I was working on XDL for a long time. But it cannoot match my requirements fearably. Becasue on XDL, the LUT has already been located to the specific hardwares of the used device. What I need is just the pure lut level netlist.

>Either of these will show the actual elements used: LUT, DFF, singles, doubles, quads (wires) etc.

>You may also examine the primitives in FPGA_Editor.
 
I dont know whehter it's right, In my idea, the NCD of FPGA editor is precisely the same thing of XDL, right?

>Why do you wish to do this?
>What is it you are trying to do (learn)?
>Why would your design need to be "corrected" at the LUT level?
 
I am working on the hardware security of cryptography. I need to generate the dual-rail logic (each elements of the regular circuit has a mirror counterpart, which works out at an exactly opposite behavior). The regular synthesize way cannot meet it.
 In the ideal way, I need to place each pair of LUT (original and complementary LUT) into the same SLICE. If work on XDL, different LUT would probably occupy all the lut resource in each SLICE. There will no free space to place the complementary LUT.
 
But I still don't know how to use just one LUT resource in each used SLICE? Can the synthesis attribute do it? 
 
Another question is :
   I just checked the post-synthesis simulation netlist, in the title, it say:
 
// Purpose:   
//     This verilog netlist is a verification model and uses simulation
//     primitives which may not represent the true implementation of the
//     device, however the netlist is functionally correct and should not
//     be modified. This file cannot be synthesized and should only be used
//     with supported simulation tools.
 
I just don't know why  this netlist cannot be synthesized?
 
Thanks!!
 
 
Best,
Eric,
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