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pieterhuyghe
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Registered: ‎11-16-2007

How to assign a signal (string) to a generic map of a GTP in a generate statement?

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Hi all,

 

I'm busy with some modifications in an aurora link in the Virtex5. I want to make it a bit more generic so that I can use the same module in different Virtex5 devices, because one Virtex5 has 8lanes RX and 4lanes TX and the other one has just the opposite. So for this I have to modify the aurora module that is generated by Coregen. I made some VHDL code like it is shown below. I'm not 100% sure that this will synthesize correctly, but I think it should be possible. But the problem that I have now is how that I should "write" the signals for the generic mapping. Because this are the only ones that are changing through the generation of the GTP block I wanted to do this in a seperate generate. I could infact just instantiate 3 times the GTP block, but  for better reading I wanted it to do it like written below. But now I also get the following errors:

Size mismatch.  String literal "SLAVE" is of size 5 but is expected to be of size 6. (So I shouldn't say 1 to 6, but otherwise XST complains because my symbol isn't constrained)

The actual value (Signal 'TILE_CHAN_BOND_LEVEL_0_int') associated with a generic must be a globally static expression.

 

I've already searched the internet and on different forums but I couldn't find an answer to my problem.

So does anybody know how I should correctly define those symbols TILE_CHAN_BOND_MOD_x, which are infact strings? 

 

    subtype chan_bond_string is string (1 to 6);
    
    signal TILE_CHAN_BOND_LEVEL_0_int  : integer   := 0;    
    signal TILE_CHAN_BOND_LEVEL_1_int  : integer   := 0;    
    signal TILE_CHAN_BOND_MODE_0_int   : chan_bond_string;
    signal TILE_CHAN_BOND_MODE_1_int   : chan_bond_string;

 

generate_gtp_tiles: for x in 0 to NUMBER_OF_LANES/2-1 generate
        G1 : IF x < NUMBER_OF_LANES/4-1 generate
            TILE_CHAN_BOND_LEVEL_0_int <= 2*x+2;
            TILE_CHAN_BOND_LEVEL_1_int <= 2*x+3;
            TILE_CHAN_BOND_MODE_0_int  <= "SLAVE";
            TILE_CHAN_BOND_MODE_1_int  <= "SLAVE";
        end generate;
        
        G2 : IF x = NUMBER_OF_LANES/4-1 generate
            TILE_CHAN_BOND_LEVEL_0_int <= x+NUMBER_OF_LANES/2;
            TILE_CHAN_BOND_LEVEL_1_int <= x+NUMBER_OF_LANES/2+1;
            TILE_CHAN_BOND_MODE_0_int  <= "SLAVE";
            TILE_CHAN_BOND_MODE_1_int  <= "MASTER";
        end generate;
        
        G3 : IF x < NUMBER_OF_LANES/4-1 generate
            TILE_CHAN_BOND_LEVEL_0_int <= (3*NUMBER_OF_LANES/2)-2-3*x;
            TILE_CHAN_BOND_LEVEL_1_int <= (3*NUMBER_OF_LANES/2)-2-3*x;
            TILE_CHAN_BOND_MODE_0_int  <= "SLAVE";
            TILE_CHAN_BOND_MODE_1_int  <= "SLAVE";
        end generate;
        
        GTP_TILE_INST : aurora_8b10b_v5_2_GTP_TILE  
        generic map (
            --_______________________ Simulation-Only Attributes __________________
            TILE_SIM_MODE                   => SIM_MODE, 
            TILE_SIM_GTPRESET_SPEEDUP       => SIM_GTPRESET_SPEEDUP,
            TILE_SIM_PLL_PERDIV2            => SIM_PLL_PERDIV2,
            TILE_CHAN_BOND_LEVEL_0          => TILE_CHAN_BOND_LEVEL_0_int,
            TILE_CHAN_BOND_LEVEL_1          => TILE_CHAN_BOND_LEVEL_1_int,
            TILE_CHAN_BOND_MODE_0           => TILE_CHAN_BOND_MODE_0_int,
            TILE_CHAN_BOND_MODE_1           => TILE_CHAN_BOND_MODE_1_int
        ) 
        port map (
        --*************************************************************************************************            
        -------------------------------------Both GTPs in a Tile-------------------------------------------
        --*************************************************************************************************
            ------------------------ Loopback and Powerdown Ports ----------------------
            LOOPBACK0_IN                   => LOOPBACK_IN,

 

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rcingham
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8,008 Views
Registered: ‎09-09-2010
In VHDL you cannot connect signals to generics. You can connect constants to generics in the generic map.

You could have a separate instantiation under each of G1, G2, G3, or else define functions that run at compile time to convert 'x' to the correct values. I have done it, but it's a bit tricky.

------------------------------------------
"If it don't work in simulation, it won't work on the board."

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rcingham
Teacher
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8,009 Views
Registered: ‎09-09-2010
In VHDL you cannot connect signals to generics. You can connect constants to generics in the generic map.

You could have a separate instantiation under each of G1, G2, G3, or else define functions that run at compile time to convert 'x' to the correct values. I have done it, but it's a bit tricky.

------------------------------------------
"If it don't work in simulation, it won't work on the board."

View solution in original post

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pieterhuyghe
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Registered: ‎11-16-2007

Ah ok, I thought it was possible. Then I'll just instantiante three times the GTP module. Thanks for the reply...

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