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Explorer
Explorer
6,717 Views
Registered: ‎03-06-2014

How to export the directed routing constraints to the UCF file?

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Hello,

 

I am working with ISE 14.7 targeting a Virtex-5 FPGA. I manually placed and routed some components of my design. I know that those new constraints (PLACE&ROUTE) are written automatically in PCF file. But I am wondering to know how can I export the manual routing and placement constraints from FPGA Editor to the main UCF of my design??

 

In the following link it was written : " If you want to maintain both routing and placement, export the directed routing constraints to the UCF file" .... but how to do it??

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_imp_strategies_using_fpga_editor.htm

 

Kind replies are in advance appreciated.

 

Thanks and Regards,

 

 

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1 Solution

Accepted Solutions
Instructor
Instructor
12,946 Views
Registered: ‎08-14-2007

Re: How to export the directed routing constraints to the UCF file?

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Open the routed design in FPGA editor.

Select the net(s) you want to constrain.

Go to Tools --> Directed Routing Constraints...

 

A window will pop up as below.  Default is to append constraints to the end of your project UCF file.

You can also select nets within that pop-up window.

 

-- Gabor
Directed_Routing.PNG
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2 Replies
Instructor
Instructor
12,947 Views
Registered: ‎08-14-2007

Re: How to export the directed routing constraints to the UCF file?

Jump to solution

Open the routed design in FPGA editor.

Select the net(s) you want to constrain.

Go to Tools --> Directed Routing Constraints...

 

A window will pop up as below.  Default is to append constraints to the end of your project UCF file.

You can also select nets within that pop-up window.

 

-- Gabor
Directed_Routing.PNG
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Explorer
Explorer
6,698 Views
Registered: ‎03-06-2014

Re: How to export the directed routing constraints to the UCF file?

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SOLVED....!

 

Thank you so much @gszakacs (Gabor) for your guide. The problem got solved !

 

Regards,

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