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Visitor
Visitor
7,830 Views
Registered: ‎01-05-2013

How to generate a clock which can be a clock_generator of DDR3 on ML605 by coregen.

I want to generate a clock by coregen to drive DDR3 controller and DDR3 memory on ML605.  I dont know how to configure the clock to generate the clk_ref(200MHz), clk_mem(400MHz), clk_rd_base(400MHz, nobuf_varphase).

 

Could someone please tell me how to archive it? Thank you!

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Guide
Guide
7,817 Views
Registered: ‎01-23-2009

The easiest way is to use the Clocking Wizard from CoreGen/IP catalog.

 

You can ask the wizard to take in the 200MHz differential clock inputs from the ML605, and generate the outputs you want. This will instantiate the IBUFGDS for the clock input, the MMCM with the appropriate feedback, and the outputs - automatically selecting the right frequency for the VCO in the MMCM and all the dividers - along with all the clock buffers (including telling the tool you don't want a clock buffer for the last output).

 

Avrum

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Visitor
Visitor
7,805 Views
Registered: ‎01-05-2013

Thanks for your reply. Could you please tell the details of every parameters in Clocking Wizard?

When I use the clock generated by myself, I run into some problems of ddr3_phy_initialisation, ZQ calibration and timing disorder in dfi. I dont know the reasons. Could you please give me some advice how I can judge the clock generated by myself?

Thank you so much!
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Historian
Historian
7,794 Views
Registered: ‎02-25-2008


@modelsim110 wrote:
Thanks for your reply. Could you please tell the details of every parameters in Clocking Wizard? 

I believe that the Clocking Wizard has a comprehensive help file, which is much larger than the space available on a forum post.

----------------------------Yes, I do this for a living.
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Explorer
Explorer
7,777 Views
Registered: ‎04-08-2009

Hello, i did the same. I took a DDr3 Memory, which runs at 400 MHz.

Therefore you need to feed the MIG Interface with the half clock (200 MHz) and feed the clk_ref input of it.

For the sys_clk port of the MIG Controller i took 100 MHz, you can vary it but have to adjust it in the DDR3 DMC parameter.

I guess it easy to generate the 100 and 200 MHz with a DCM and feed the DDR3 MIG Controller with it.

 

Next you need to set the MIG parameters that they accept the 100 MHz on the sys_clk input.

Therefore you need to adjust the MIG parameters as following:

      MMCM_ADV_BANDWIDTH  : string                        := "OPTIMIZED";
                                        -- MMCM programming algorithm
      CLKFBOUT_MULT_F     : integer                       := 8;
                                        -- write PLL VCO multiplier.
      DIVCLK_DIVIDE       : integer                       := 1;
                                        -- write PLL VCO divisor.
      CLKOUT_DIVIDE       : integer                       := 2;
                                        -- VCO output divisor for fast (memory) clocks.
      nCK_PER_CLK         : integer                       := 2;

 So the MIG always puts you an output clock to drive your logic, which is recommended.

But its always the half clock 200 MHz (DDR3 runs at 400 MHz).

 

If your logic is slower like in my case, you need to do a Clock domain crossing.

Easiest way: use dual clocked FiFos.

 

 

 

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Visitor
Visitor
7,754 Views
Registered: ‎01-05-2013

Hello! I am very glad to receive your help! Thank you!

What is the sys_clk ? Why do you set it as 100MHz? According to uf406 figure1-47(page 84), I saw that system clock freq = memory clock freq as an input of MMCM.

I configured pll as following. The CLK_IN_P/N is differential 200MHz, BUFG.
MMCM0_INST : mmcm_module
generic map (
C_BANDWIDTH => "OPTIMIZED",
C_CLKFBOUT_MULT_F => 6.000,
C_CLKFBOUT_PHASE => 0.0,
C_CLKFBOUT_USE_FINE_PS => FALSE,
C_CLKIN1_PERIOD => 5.000000,
C_CLKOUT0_DIVIDE_F => 12.000,
C_CLKOUT0_DUTY_CYCLE => 0.5,
C_CLKOUT0_PHASE => 0.0000,
C_CLKOUT1_DIVIDE => 6,
C_CLKOUT1_DUTY_CYCLE => 0.5,
C_CLKOUT1_PHASE => 0.0000,
C_CLKOUT2_DIVIDE => 3,
C_CLKOUT2_DUTY_CYCLE => 0.5,
C_CLKOUT2_PHASE => 0.0000,
C_CLKOUT3_DIVIDE => 3,
C_CLKOUT3_DUTY_CYCLE => 0.5,
C_CLKOUT3_PHASE => 0.0000,
C_CLKOUT4_DIVIDE => 1,
C_CLKOUT4_DUTY_CYCLE => 0.5,
C_CLKOUT4_PHASE => 0.0,
C_CLKOUT4_CASCADE => false,
C_CLKOUT5_DIVIDE => 1,
C_CLKOUT5_DUTY_CYCLE => 0.5,
C_CLKOUT5_PHASE => 0.0,
C_CLKOUT6_DIVIDE => 1,
C_CLKOUT6_DUTY_CYCLE => 0.5,
C_CLKOUT6_PHASE => 0.0,
C_CLKOUT0_USE_FINE_PS => FALSE,
C_CLKOUT1_USE_FINE_PS => FALSE,
C_CLKOUT2_USE_FINE_PS => FALSE,
C_CLKOUT3_USE_FINE_PS => TRUE,
C_CLKOUT4_USE_FINE_PS => false,
C_CLKOUT5_USE_FINE_PS => false,
C_CLKOUT6_USE_FINE_PS => false,
C_COMPENSATION => "ZHOLD",
C_DIVCLK_DIVIDE => 1,
C_REF_JITTER1 => 0.010,
C_CLKIN1_BUF => true,
C_CLKFBOUT_BUF => false,
C_CLKOUT0_BUF => false,
C_CLKOUT1_BUF => false,
C_CLKOUT2_BUF => false,
C_CLKOUT3_BUF => false,
C_CLKOUT4_BUF => false,
C_CLKOUT5_BUF => false,
C_CLKOUT6_BUF => false,
C_CLOCK_HOLD => false,
C_STARTUP_WAIT => false,
C_EXT_RESET_HIGH => 1,
C_FAMILY => "virtex6"
)

CLK_OUT0=100MHz, CLK_OUT1=200MHz(clk_ref),CLK_OUT2=400MHz(clk_mem),CLK_OUT3=400MHz(clk_rd_base). Is it right? Or could you please tell me your configuration of pll in details?

Thank you very much!
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Explorer
Explorer
7,707 Views
Registered: ‎04-08-2009

Hello, yes this should work.

By the way if you simulate the DDR memory in Modelsim then you get many many errors if you got a wrong clock anyway!

So i really suggest to you to simulate the DDR3 memory also.

 

By the way there is no post place and route simulation with the DDR3 Model.

 

But errors about wrong clock will also appear in the behavioral simulation.

 

I guess you can also simulate it within ISIM but i dont have tested it.

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