05-26-2011 09:10 AM
I have a custom board with Virtex 6 LX240T (1156) and a High Speed ADC (3 GSPS, 8 bit) on it. Now I want to evaluate if I can do IQ-Demodulation inside the FPGA of one ADC channel. The data is coming in at 750 MHz (4 Byte at one tick).
Is there any tool or guide how I can validate if it is possible to implement it on this specific Virtex 6?
I appreciate any hint!
05-26-2011 10:05 AM
so basicaly you need to do a design from scratch,
a long road
get the adc working first,
prove the adc works as expected
design a IQ demodulator
see the logi cores for help
Easy Ah !
05-26-2011 10:38 AM
actually it seems to be easy every time I read a Xilinx Tutorial etc. but mostly it is not..
The ADC works, so I get the data as I want it! But I am not sure if I can handle the demodulation (which basically is similar to DDC) at this high data rate (3 GB/s). If not I have to do the demodulation in analog domain and capture twoi channels at a lower sampling rate.
So, how could I estimate if my digital demodulation approach will work?
05-26-2011 10:49 AM
so you have captured the data into the FPGA,
so you now have data in the fpga, on a single clock ?
what width is the data and what clock is the data in the FPGA
you imply that you have a digital demodulator aproach already worked out,
is that correct ?
05-26-2011 11:59 AM
The data is captured at 375 MHz: 4 parallel ADC-ports á 8 bit diff. signal => 64 bit
Then the data is stored into four registers (each 32 bit) @ 375/2 MHz to work with.
I have to say the ADC-IF is not implemented by myself, it seems that it just uses half rate @ 1.5GSPS instead of 3GSPS!?
I have no specific implementation for the demodulator right now, but as I read it is similar to DDC. The signal has to be multiplied by sin and cos wave and the outcoming I & Q channels have to be filtered (basically)
Thanks for your time!
05-26-2011 12:17 PM
so you have 4 parallel streams inside the fpga ?
each 8 bits wide, running at what clock frequency ?
05-26-2011 12:30 PM
05-26-2011 01:21 PM
inside the FPGA its 16 bits wide ?
the adc is only 8 bits wide, where does the extra data width come from ?
05-26-2011 02:27 PM - edited 05-26-2011 03:00 PM
Sorry, now I am clear about it: the data is 64 bit (8 samples using falling and rising clock edge) @ 375 MHz, then in the next cycle I have 128 bit. These 128 bit are splitted up into 8 parallel streams á 16 bit (two adjacent samples) @ 375/2 MHz!
The ADC gives 4 samples at a clock of 750 MHz, this makes 32 bit @ 750 MHz or 64 bit using DDR @ 375 MHz.with the FPGA. Then there is a kind of DeMUX to make it 128 bit (16 samples) @ 375/2 MHz and splitting it up to 8 x 16 bit!
05-26-2011 11:48 PM
your saying you manage to get 16 bits of data from one 8 bit ADC ?
or do you mean two 8 bit streams ?
so you have how many 8 bit streams at what clock frequency ?
05-27-2011 11:01 AM
Sorry, I hope I can make it clear:
I have a ADC, actually there are two 8bit ADCs inside, so there are two samples at 1.5GHz at the output. The ADC has a kind of buffer for thes two samples. There are four 8bit output ports at the ADC, so the benefit is I can capture 4 samples (32 bit) at 750 MHz. But I capture it with a 375 MHz clock at rising and falling clock edge (DDR) to the FPGA, inside the FPGA I do actually the same as in the ADC, buffering and capturing at half the clock rate..
At the end I have these 8x16bits in parallel at 375/2 MHz, that are 16 samples. I have two adjacent samples (16bit) at each of the 8 lines to bring them into fifo's.
For demodulation I will have to adapt these to 16 streams each 8bit (one sample) at the same clock as before, 375/2 MHz.
The question is, if I can handle them, I need to multiply the incoming signal with sin and cos in parallel (split signal) and then filter both I and Q channels!
Hope this makes it clear. Thank you.
05-27-2011 11:18 AM
so you have lets say
adc at M samples per second , 8 bits wide.
inside the FPGA this is split into N parallel streams each 8 bits wide, at a clock speed of 188 MHz ( ish )
so to demodulate that to I/Q
brute force, you need N DDC cores running at 188 MHz.
you need to phase shift the start phase to each core by the ( C* phase step / N) , where C is 0 to N-1
and the phase step needs to be N times the mulitplying frequency..
The v6 should run at 375 Mhz, so you could time multiplex the cores, and only need N/2 instances of the DDC core.
Depending upon the size of the sin / cos used, the size of the I/Q could be 12 or more bits.
thats a lot of data coming out the core.
the normal answwer is to decimate, CIC filter et all.
so to answer your question, yes the core you want will easily fit in a virtex 6,
unless you have lots of other stuff,
05-27-2011 12:41 PM - edited 05-27-2011 01:33 PM
So far there is not much implemented on the V6.
After IQ-Demodulation there will be some processing to reduce the data. Thanks also for the advice for the CIC, I will have a look on it!
So the DDC core itself is not that big? In my case N will be 16 and I need I and Q channel that makes 32 at the end!
Further remarks/suggestions are welcome..now I will give it a try.