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Visitor korkikian
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11,769 Views
Registered: ‎05-06-2013

IODelay fabric to fabric

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Hello,

 

I am trying to use IODELAY element to create pulse signal. Lets assume that the minimum pulse width is 10ns, however I need a resolution of 0.1ns. The initial idea was to use IODELAY internally to delay one signal, invert it and add with the initial signal. In this case I will have a required resolution.

 

I am using Virtex-5 FPGA board. According to the user manual (Table 7-6 IODELAY configuration supported) when IODELAY is in IDELAY mode then we can use fabric as a source for DATAIN and fabric as a destination of DATAOUT. I thought that I can give internally generated signal to IODELAY and get a delayed signal that can be used internally as well. Unfortunately, I could not make it.

 

Do you have any clue if I am completely lost in documentation and IODELAY can not be used in such way or there is another possible problem? I am instantinating IDELAYCTRL as well. DATAIN is supplied directly by the register output.

 

If you have any comments I would really appreciate it.

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Visitor korkikian
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19,202 Views
Registered: ‎05-06-2013

Re: IODelay fabric to fabric

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I finally could route IODELAY to work with internal signals. I had to double check the mapping since Xilinx tools connected ILOGIC and IODELAY directly instead of placing one register in between. That caused all the problems with constant low signal.

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Visitor korkikian
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Registered: ‎05-06-2013

Re: IODelay fabric to fabric

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Well, apparently documentation says: "The IODELAY can also be used to add additional static or variable delay to an internal
path (within the FPGA fabric). However, when IODELAY is used that way, this device is no longer available to
the associated I/O for input or output path delays." Does it mean that I can't use IOs anymore?
Instructor
Instructor
11,733 Views
Registered: ‎08-14-2007

Re: IODelay fabric to fabric

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@korkikian wrote:
Well, apparently documentation says: "The IODELAY can also be used to add additional static or variable delay to an internal
path (within the FPGA fabric). However, when IODELAY is used that way, this device is no longer available to
the associated I/O for input or output path delays." Does it mean that I can't use IOs anymore?

No, the IO is still available, but you can't use it with a delay.  Basically each IODELAY element is associated

with a particular IO.  If that IO doesn't need a delay, then its IODELAY should be available for use in the

fabric (haven't tried this myself).  On the other hand, if you don't need a lot of these IODELAYs, then you

might have enough unused IOs (including unbonded IOs) that you don't need to "steal" an IODELAY from

a pin you're using in the design.

-- Gabor
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Visitor korkikian
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11,723 Views
Registered: ‎05-06-2013

Re: IODelay fabric to fabric

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@gszakacs wrote:

No, the IO is still available, but you can't use it with a delay.  Basically each IODELAY element is associated

with a particular IO.  If that IO doesn't need a delay, then its IODELAY should be available for use in the

fabric (haven't tried this myself).  On the other hand, if you don't need a lot of these IODELAYs, then you

might have enough unused IOs (including unbonded IOs) that you don't need to "steal" an IODELAY from

a pin you're using in the design.


Thank you for replay.

Indeed, I could use IODELAY that routes fabric to fabric signal with the IDELAY_TYPE = "FIXED", however, when I switch to IDELAY_TYPE = "VARIABLE" then the signal is always logic 0.

 

At the moment I am trying to understand this problem =)


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Visitor korkikian
Visitor
19,203 Views
Registered: ‎05-06-2013

Re: IODelay fabric to fabric

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I finally could route IODELAY to work with internal signals. I had to double check the mapping since Xilinx tools connected ILOGIC and IODELAY directly instead of placing one register in between. That caused all the problems with constant low signal.

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