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Adventurer
Adventurer
8,702 Views
Registered: ‎03-05-2009

ISERDES clkdiv and Qx?

Hello,

 

I For the first time, I am working on a project that needs ISERDES, and there is something I do not manage to understand.

 

- The CLK signal is used to catch the input data : no pb with that!

- The CLKDIV (which in my case is 6 time slower than CLK) is said to command the deserialiser.

 

Also I was attempting to see an update of ISERDES Qx outputs on CLKDIV events (rising or falling)

or, in other words, to have the "Q6Q5Q4Q3Q2Q1" words equal to the 6 data received during each CLKDIV period...

 

But it seems not to be the case...

 

In behavioral simulation the  "Q6Q5Q4Q3Q2Q1" are not synchronized with the CLKDIV period

 

 

For example, if I have the DATA os follow, my OUPUTS are:

 

                        _________                      ________                   _________                     ____

CLKDIV      __|                  |_________ |                 |________ |                   |_________|       

 

DATA               A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R   

                   ______________________  ________________  ___________________  _____

OUTputs    ______________________X____CDEFGH ____X_____ IJKLMN   _____X____

 

While attempting [ABCDEF], [GHIJKL], [MNOPQR], ....

 

What did I miss?

 

Thank you for your help,

 

Alexandre

 

 

 

 

 

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8 Replies
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Instructor
Instructor
8,698 Views
Registered: ‎07-21-2009

You don't specify which FPGA family you are targeting.  They aren't all the same in every detail.

 

Search the appropriate docs of the selected FPGA family for key words: "word framing" and "bitslip".

 

-- Bob Elkind

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2. Search the forums (and search the web) for similar topics.
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Adventurer
Adventurer
8,694 Views
Registered: ‎03-05-2009

Thank you for your help !

 

I have already surched for that with no success.

 

In the Virtex 6 ug361.pdf it is said that CLKDIV "drives the output of the serial-to-parallel
converter".

 

I also read the BITSLIP option description (page 141-142),but in my case, it is wired to '0' => NO shift on the output...

 

I do not understand what is happening...

 

Alex

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Instructor
Instructor
8,691 Views
Registered: ‎07-21-2009

You can perform word framing in the fabric logic, or you can perform word framing in the ISERDES block.  If you perform word framing in the ISERDES block, you will need to provide support logic to drive the BITSLIP input to the ISERDES block.

 

Do you understand from UG361 how BITSLIP works?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Adventurer
Adventurer
8,680 Views
Registered: ‎03-05-2009

Yes, I understand how it works !

 

As it is shown on ug361 p143 figure 3-15, If no bislip is performed, the Qx data presented at the iserdes Output are aligned with the CLKDIV :

 

In the example of the figure 3-15 the input data are, for each DIVCLK period "CDAB" .

And if BITSLIP = '0', the Q1-Q4 output word is "CDAB" (what I would expect).

 

In my case, BITSLIP is = '0' and I do not have "CDAB" but "DABC".

Like if a shifting was performed even woth no BITSLIP.

 

AdcClock_I_Isrds_Master : ISERDESE1
generic map (
   SERDES_MODE       => "MASTER",		-- 
   INTERFACE_TYPE    => "NETWORKING",	-- 
   IOBDELAY	     => "IBUF",			-- 
   DATA_RATE 	     => "SDR", 			-- 
   DATA_WIDTH 	     => 6,					--
   DYN_CLKDIV_INV_EN => FALSE, 			-- 
   DYN_CLK_INV_EN    => FALSE, 			-- 
   NUM_CE	     => 1, 				-- 
   OFB_USED	     => FALSE 			-- 
   )
port map (
   D		     => BitClk,		
   DDLY		     => IntBitClk_Ddly, 		
   DYNCLKDIVSEL	     => Low,    
   ...
   BITSLIP	     => Low,
   ...
);

 

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Instructor
Instructor
8,675 Views
Registered: ‎07-21-2009

If you are generating CLKDIV and serial DATA signals with a known timing relationship, then this should ensure a consistent word framing at the output of the ISERDES blocks.  If word framing isn't correct, a reasonable explanation would be that the number of register stages in the ISERDES block is different than what you expected.

 

Have you checked ISERDES output results both in simulation and in physical hardware?  If so, are the results utterly consistent?

 

The block diagrams in Xilinx docs are often simplified functional representations.  Often, they are not representative of physical implementation at the transistor level.  This might explain register delays inside the ISERDES block which don't match your expectation.

 

If my explanation is correct (and keep in mind -- I am not a Xilinx employee, I do not have first-hand knowledge of Xilinx' secrets), would you prefer to re-time the CLKDIV signal or would you prefer to clean up the word framing with a few fabric registers?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Adventurer
Adventurer
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Registered: ‎03-05-2009

I am dealing with the BITSLIP option, and can not find a clear explanation ...

 

If we have :

chrono.jpg

 

With no BITSLIP, the output frames will be "ABCDEFGH", "IJKLMNOP", etc...

 

If bitslip has been up for 1 clkdiv, what will be the outputs : "BCDEFGHA" or "BCDEFGHI"?

 

Alex

 

 

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Instructor
Instructor
8,654 Views
Registered: ‎07-21-2009

Assuming the sequence "ABCDEFGH", "IJKLMNOP" repeats, the correct answer is "BCDEFGHI".  This allows bitslip function to be useful for data words wider than the ISERDES block.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor
Visitor
8,560 Views
Registered: ‎02-27-2012


@guilvard wrote:

Hello,

 

I For the first time, I am working on a project that needs ISERDES, and there is something I do not manage to understand.

 

- The CLK signal is used to catch the input data : no pb with that!

- The CLKDIV (which in my case is 6 time slower than CLK) is said to command the deserialiser.

 

Also I was attempting to see an update of ISERDES Qx outputs on CLKDIV events (rising or falling)

or, in other words, to have the "Q6Q5Q4Q3Q2Q1" words equal to the 6 data received during each CLKDIV period...

 

But it seems not to be the case...

 

In behavioral simulation the  "Q6Q5Q4Q3Q2Q1" are not synchronized with the CLKDIV period

 

 

For example, if I have the DATA os follow, my OUPUTS are:

 

                        _________                      ________                   _________                     ____

CLKDIV      __|                  |_________ |                 |________ |                   |_________|       

 

DATA               A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R   

                   ______________________  ________________  ___________________  _____

OUTputs    ______________________X____CDEFGH ____X_____ IJKLMN   _____X____

 

While attempting [ABCDEF], [GHIJKL], [MNOPQR], ....

 

What did I miss?

 

Thank you for your help,

 

Alexandre

 

 

 

 

 



I have the same result as you describe . According to my understanding of UG361,the result should be [ABCDEFG,] [HIJKLMN] ,but in the result of the simulation The output of Q port is [CDEFGH ], [IJKLMN ].

I do not know which one is right. Is my understanding error or the simulation result ,or both of them are fault ?

Thank you  

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