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orangepeace
Explorer
Explorer
7,631 Views
Registered: ‎11-02-2011

If not constraint IO standard in .ucf, what IO standard is.....

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Hi all,

 

   In the .ucf, if I define the following constraint,

 

  NET "ad<17>" LOC = "L3" | IOSTANDARD = LVCMOS33 | SLEW=FAST ;

 

  The IO standard should be LVCMOS33. But if I donot define the IOSTANDARD here, what the IO standard should be?

 

Thanks.

Best Regards.

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jschimek
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007
It can vary by device, but for Virtex-6 its LVCMOS25 12mA Fast for single ended and LVDS_25 for differential. If you look under the SelectIO user guide for your specific family, you can find the default. Similarly the configuration user guide will have this info.

Regards,
Jon

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rcingham
Teacher
Teacher
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Registered: ‎09-09-2010

What FPGA?

Which package?

 


------------------------------------------
"If it don't work in simulation, it won't work on the board."
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jschimek
Xilinx Employee
Xilinx Employee
9,475 Views
Registered: ‎08-02-2007
It can vary by device, but for Virtex-6 its LVCMOS25 12mA Fast for single ended and LVDS_25 for differential. If you look under the SelectIO user guide for your specific family, you can find the default. Similarly the configuration user guide will have this info.

Regards,
Jon

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kren
Moderator
Moderator
7,603 Views
Registered: ‎08-21-2007

You can also get to knew the default IO standard in pinout report.

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ywu
Xilinx Employee
Xilinx Employee
7,596 Views
Registered: ‎11-28-2007

Just wanted to add that for 7 series FPGAs, you must explicitly specify IOSTANDARDs for all IOs (by the way, I think this is a good practice for other FPGA families as well), otherwise you will get an error in bitgen.

Cheers,
Jim
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