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Registered: ‎07-24-2008

Is GCLK pin connected to IBUFG?

Hi all,


    My project has only one clk which is from external of FPGA. I assigns it to a GCLK pin. Does this pin connect to IBUFG automatically? As far as I am concerned, when I use DCM with Core Generator, it will generate an IBUFG. That is:



Then the clock can enter global clock net.


If I donot use DCM, is it GCLK-->IBUFG-->BUFG or others?




Best Regards.

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Registered: ‎11-29-2007

The tools will automatically insert clock buffers if they detect that an input signal is used as a clock for synchronous elements.




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Xilinx Employee
Xilinx Employee
Registered: ‎01-03-2008

You used the term GCLK, but this is just a label and not an element in the device.  This is a common misunderstanding from new users.


In your system you will have an external clock (this may either by a single ended IO standard like LVCMOS25 or a differential IO standard like LVDS) that must be applied as an input to the FPGA.   Since clocks require special handling to ensure that the overal delay and skew across all of the endpoints is low each FPGA has dedicated routing and clocking elements (DCM, PLL, MMCM, BUFG, etc) to be able to meet these needs.


There actually is no difference between using an IBUFG/IBUFGDS or an IBUF/IBUFDS in a netlist.  The two names exist solely for legacy reasons and in order to impress upon the reader that that clocks must come in on only certain pins the documentation will use the IBUFG or IBUFGDS element to reinforce this message.    


Each FPGA family has a Pinout User Guide that documents which IO must be used for clock inputs to be able to use the dedicated routing resources from the IO to the clocking elements in the device.  The clock capable IO pin names include a designation of  "GC", "CC", "MRCC" or  "SRCC" that describes the connectivity in the device.  See the FPGA family pinout and clocking user guides for more information on the differences between these pins.


If you need a DCM/PLL/MMCM to remove the clock insertion delay or to generate additional frequencies then connections should be:

    clock port -> IBUFG -> DCM -> BUFG

if you don't need this then your can use the simpler:

    clock port -> IBUFG -> BUFG


The clock port will need to have a LOC constraint added to place in on a correct "GC" type IO pin.  For instance in your UCF file

    NET "clock_port" LOC = AA11;

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Registered: ‎03-08-2012

actually am using spartan-3AN family.iam using an external clock of initially for test bench we are dividing it by 3.

so i need vhdl code for that clock division using dcm and how can i interface these divided clock to the i/o pins.

i.e.,frm 25MHZ clock to i/o pins through dcm. whether there is any configuration registers there to set them. can any one solve me....

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