In my design,i use 4 chips of xc6vsx475t .Every piece of FPGA use the platform configuration with the chip of JS28F256P30T. And i use JTAG chain to string the 4 FPGAs. There are some question that i can not determin.
1.When i download code using JTAG chain, will conflict be resulted.
2.From the ug360,"Additionally, if the chain is large (three devices or more), TMS and TCK should be buffered to ensure that they have sufficient drive strength at all receivers, and the voltage at logic High must be compatible with all devices in the chain." can you reconmmend a chip of buffer ? Is the chip of SN74LVC3G07 as a buffer ok?