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guilvard
Adventurer
Adventurer

‎02-15-2011 02:10 AM

7,166 Views
Registered: ‎03-05-2009

Map Error

Hello,

 

I am working on a vhdl design to read / write data from / to a DDR3 memory.

For this purpose I implemented a MIG V3.6 module. (behavior validated by simulation)

 

The design has to be implemented on a Virtex6 developement board from Hitech Global : Board

 

These IO used by the DDR3 are :

 

 

entity Main is   
  port(
       ….
      ddr3_dq	         : inout std_logic_vector(DQ_WIDTH-1 downto 0);
      ddr3_dm	         : out   std_logic_vector(DM_WIDTH-1 downto 0);
      ddr3_addr       	 : out   std_logic_vector(ROW_WIDTH-1 downto 0);
      ddr3_ba      	 : out   std_logic_vector(BANK_WIDTH-1 downto 0);
      ddr3_ras_n	 : out   std_logic;
      ddr3_cas_n    	 : out   std_logic;
      ddr3_we_n          : out   std_logic;
      ddr3_reset_n 	 : out   std_logic;
      ddr3_cs_n    	 : out   std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
      ddr3_odt       	 : out   std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
      ddr3_cke        	 : out   std_logic_vector(CKE_WIDTH-1 downto 0);
      ddr3_dqs_p    	 : inout std_logic_vector(DQS_WIDTH-1 downto 0);
      ddr3_dqs_n   	 : inout std_logic_vector(DQS_WIDTH-1 downto 0);
      ddr3_ck_p    	 : out   std_logic_vector(CK_WIDTH-1 downto 0);
      ddr3_ck_n   	 : out   std_logic_vector(CK_WIDTH-1 downto 0)
    );
end Main;

 

 

The UCF generated by the MIG_Core_Generator defines Constraints on the IO type.

 

 

NET  "ddr3_dq[*]"        IOSTANDARD = SSTL15_T_DCI;
NET  "ddr3_addr[*]"      IOSTANDARD = SSTL15;
NET  "ddr3_ba[*]"        IOSTANDARD = SSTL15;
NET  "ddr3_ras_n"        IOSTANDARD = SSTL15;
NET  "ddr3_cas_n"        IOSTANDARD = SSTL15;
NET  "ddr3_we_n"         IOSTANDARD = SSTL15;
NET  "ddr3_reset_n"      IOSTANDARD = SSTL15;
NET  "ddr3_cke[*]"       IOSTANDARD = SSTL15;
NET  "ddr3_odt[*]"       IOSTANDARD = SSTL15;
NET  "ddr3_cs_n[*]"      IOSTANDARD = SSTL15;
NET  "ddr3_dm[*]"        IOSTANDARD = SSTL15;
NET  "ddr3_dqs_p[*]"     IOSTANDARD = DIFF_SSTL15_T_DCI;
NET  "ddr3_dqs_n[*]"     IOSTANDARD = DIFF_SSTL15_T_DCI;
NET  "ddr3_ck_p[*]"      IOSTANDARD = DIFF_SSTL15;
NET  "ddr3_ck_n[*]"      IOSTANDARD = DIFF_SSTL15;

 

As i use a develoment board, the IO's used to communicate with the DDR3 are fixed and can not be changed:

 

 

NET  "ddr3_dq[0]"                                LOC = "AL39" ;          #Bank 14
NET  "ddr3_dq[1]"                                LOC = "AK39" ;          #Bank 14
NET  "ddr3_dq[2]"                                LOC = "AG33" ;          #Bank 14
NET  "ddr3_dq[3]"                                LOC = "AF32" ;          #Bank 14
NET  "ddr3_dq[4]"                                LOC = "AL40" ;          #Bank 14
NET  "ddr3_dq[5]"                                LOC = "AK40" ;          #Bank 14
NET  "ddr3_dq[6]"                                LOC = "AF36" ;          #Bank 14
NET  "ddr3_dq[7]"                                LOC = "AF35" ;          #Bank 14
NET  "ddr3_dq[8]"                                LOC = "AL41" ;          #Bank 14
NET  "ddr3_dq[9]"                                LOC = "AG36" ;          #Bank 14
NET  "ddr3_dq[10]"                               LOC = "AM42" ;          #Bank 14
NET  "ddr3_dq[11]"                               LOC = "AL42" ;          #Bank 14
NET  "ddr3_dq[12]"                               LOC = "AK37" ;          #Bank 14
NET  "ddr3_dq[13]"                               LOC = "AJ35" ;          #Bank 14
NET  "ddr3_dq[14]"                               LOC = "AJ38" ;          #Bank 14
NET  "ddr3_dq[15]"                               LOC = "AG34" ;          #Bank 14
NET  "ddr3_dq[16]"                               LOC = "AH40" ;          #Bank 14
NET  "ddr3_dq[17]"                               LOC = "AG38" ;          #Bank 14
NET  "ddr3_dq[18]"                               LOC = "AH41" ;          #Bank 14
NET  "ddr3_dq[19]"                               LOC = "AG42" ;          #Bank 14
NET  "ddr3_dq[20]"                               LOC = "AG39" ;          #Bank 14
NET  "ddr3_dq[21]"                               LOC = "AF39" ;          #Bank 14
NET  "ddr3_dq[22]"                               LOC = "AG41" ;          #Bank 14
NET  "ddr3_dq[23]"                               LOC = "AF40" ;          #Bank 14
NET  "ddr3_dq[24]"                               LOC = "AE34" ;          #Bank 15
NET  "ddr3_dq[25]"                               LOC = "AE35" ;          #Bank 15
NET  "ddr3_dq[26]"                               LOC = "AB37" ;          #Bank 15
NET  "ddr3_dq[27]"                               LOC = "AB38" ;          #Bank 15
NET  "ddr3_dq[28]"                               LOC = "AB39" ;          #Bank 15
NET  "ddr3_dq[29]"                               LOC = "AA40" ;          #Bank 15
NET  "ddr3_dq[30]"                               LOC = "AC38" ;          #Bank 15
NET  "ddr3_dq[31]"                               LOC = "AA41" ;          #Bank 15
NET  "ddr3_dq[32]"                               LOC = "AE38" ;          #Bank 15	
NET  "ddr3_dq[33]"                               LOC = "AD38" ;          #Bank 15
NET  "ddr3_dq[34]"                               LOC = "AB36" ;          #Bank 15
NET  "ddr3_dq[35]"                               LOC = "AE32" ;          #Bank 15
NET  "ddr3_dq[36]"                               LOC = "AD37" ;          #Bank 15
NET  "ddr3_dq[37]"                               LOC = "AD41" ;          #Bank 15
NET  "ddr3_dq[38]"                               LOC = "AB32" ;          #Bank 15
NET  "ddr3_dq[39]"                               LOC = "AB33" ;          #Bank 15
NET  "ddr3_dq[40]"                               LOC = "AD40" ;          #Bank 15
NET  "ddr3_dq[41]"                               LOC = "AD36" ;          #Bank 15
NET  "ddr3_dq[42]"                               LOC = "AD42" ;          #Bank 15
NET  "ddr3_dq[43]"                               LOC = "AE42" ;          #Bank 15
NET  "ddr3_dq[44]"                               LOC = "AF42" ;          #Bank 15
NET  "ddr3_dq[45]"                               LOC = "AF41" ;          #Bank 15
NET  "ddr3_dq[46]"                               LOC = "AC34" ;          #Bank 15
NET  "ddr3_dq[47]"                               LOC = "AC33" ;          #Bank 15
NET  "ddr3_dq[48]"                               LOC = "W37" ;           #Bank 16
NET  "ddr3_dq[49]"                               LOC = "Y37" ;           #Bank 16
NET  "ddr3_dq[50]"                               LOC = "U37" ;           #Bank 16
NET  "ddr3_dq[51]"                               LOC = "U38" ;           #Bank 16
NET  "ddr3_dq[52]"                               LOC = "W36" ;           #Bank 16
NET  "ddr3_dq[53]"                               LOC = "V36" ;           #Bank 16
NET  "ddr3_dq[54]"                               LOC = "U42" ;           #Bank 16
NET  "ddr3_dq[55]"                               LOC = "U41" ;           #Bank 16
NET  "ddr3_dq[56]"                               LOC = "AA36" ;          #Bank 16
NET  "ddr3_dq[57]"                               LOC = "U39" ;           #Bank 16
NET  "ddr3_dq[58]"                               LOC = "V39" ;           #Bank 16
NET  "ddr3_dq[59]"                               LOC = "W35" ;           #Bank 16
NET  "ddr3_dq[60]"                               LOC = "V35" ;           #Bank 16
NET  "ddr3_dq[61]"                               LOC = "Y42" ;           #Bank 16
NET  "ddr3_dq[62]"                               LOC = "Y32" ;           #Bank 16
NET  "ddr3_dq[63]"                               LOC = "U33" ;           #Bank 16
NET  "ddr3_addr[12]"                             LOC = "K32" ;           #Bank 25
NET  "ddr3_addr[11]"                             LOC = "N28" ;           #Bank 25
NET  "ddr3_addr[10]"                             LOC = "P28" ;           #Bank 25
NET  "ddr3_addr[9]"                              LOC = "K35" ;           #Bank 25
NET  "ddr3_addr[8]"                              LOC = "K34" ;           #Bank 25
NET  "ddr3_addr[7]"                              LOC = "L31" ;           #Bank 25
NET  "ddr3_addr[6]"                              LOC = "L32" ;           #Bank 25
NET  "ddr3_addr[5]"                              LOC = "J37" ;           #Bank 25
NET  "ddr3_addr[4]"                              LOC = "N29" ;           #Bank 25
NET  "ddr3_addr[3]"                              LOC = "N30" ;           #Bank 25
NET  "ddr3_addr[2]"                              LOC = "H39" ;           #Bank 25
NET  "ddr3_addr[1]"                              LOC = "H38" ;           #Bank 25
NET  "ddr3_addr[0]"                              LOC = "L35" ;           #Bank 25
NET  "ddr3_ba[2]"                                LOC = "L36" ;           #Bank 25
NET  "ddr3_ba[1]"                                LOC = "J38" ;           #Bank 25
NET  "ddr3_ba[0]"                                LOC = "K37" ;           #Bank 25
NET  "ddr3_ras_n"                                LOC = "L37" ;           #Bank 25
NET  "ddr3_cas_n"                                LOC = "H40" ;           #Bank 25
NET  "ddr3_we_n"                                 LOC = "H41" ;           #Bank 25
NET  "ddr3_reset_n"                              LOC = "M34" ;           #Bank 25
NET  "ddr3_cke[0]"                               LOC = "K39" ;           #Bank 25
NET  "ddr3_odt[0]"                               LOC = "M31" ;           #Bank 25
NET  "ddr3_cs_n[0]"                              LOC = "M33" ;           #Bank 25
NET  "ddr3_dm[0]"                                LOC = "AM41" ;          #Bank 14
NET  "ddr3_dm[1]"                                LOC = "AJ41" ;          #Bank 14
NET  "ddr3_dm[2]"                                LOC = "AF34" ;          #Bank 14
NET  "ddr3_dm[3]"                                LOC = "AB41" ;          #Bank 15
NET  "ddr3_dm[4]"                                LOC = "AC40" ;          #Bank 15
NET  "ddr3_dm[5]"                                LOC = "AE40" ;          #Bank 15
NET  "ddr3_dm[6]"                                LOC = "Y39" ;           #Bank 16
NET  "ddr3_dm[7]"                                LOC = "Y40" ;           #Bank 16
#NET  "sys_clk"                                  LOC = "E14" ;           #Bank 35
#NET  "clk_ref"                                  LOC = "E14" ;           #Bank 35
#NET  "sda"                                      LOC = "F12" ;           #Bank 35
#NET  "scl"                                      LOC = "E12" ;           #Bank 35
#NET  "sys_rst"                                  LOC = "A16" ;           #Bank 35
#NET  "phy_init_done"                            LOC = "B16" ;           #Bank 35
NET  "ddr3_dqs_p[0]"                             LOC = "AH39" ;          #Bank 14
NET  "ddr3_dqs_n[0]"                             LOC = "AJ40" ;          #Bank 14
NET  "ddr3_dqs_p[1]"                             LOC = "AF37" ;          #Bank 14
NET  "ddr3_dqs_n[1]"                             LOC = "AG37" ;          #Bank 14
NET  "ddr3_dqs_p[2]"                             LOC = "AJ42" ;          #Bank 14
NET  "ddr3_dqs_n[2]"                             LOC = "AK42" ;          #Bank 14
NET  "ddr3_dqs_p[3]"                             LOC = "AE33" ;          #Bank 15
NET  "ddr3_dqs_n[3]"                             LOC = "AD33" ;          #Bank 15
NET  "ddr3_dqs_p[4]"                             LOC = "AA42" ;          #Bank 15
NET  "ddr3_dqs_n[4]"                             LOC = "AB42" ;          #Bank 15
NET  "ddr3_dqs_p[5]"                             LOC = "AC35" ;          #Bank 15
NET  "ddr3_dqs_n[5]"                             LOC = "AB34" ;          #Bank 15
NET  "ddr3_dqs_p[6]"                             LOC = "AA35" ;          #Bank 16
NET  "ddr3_dqs_n[6]"                             LOC = "Y35" ;           #Bank 16
NET  "ddr3_dqs_p[7]"                             LOC = "V38" ;           #Bank 16
NET  "ddr3_dqs_n[7]"                             LOC = "W38" ;           #Bank 16
NET  "ddr3_ck_p[0]"                              LOC = "P27" ;           #Bank 25
NET  "ddr3_ck_n[0]"                              LOC = "R27" ;           #Bank 25

 

 


I tried to implement this module, but with no success...

I have errors on the MAP process :

 

 

 

Section 1 - Errors
------------------
ERROR:Place:899 - The following IOBs use the Digitally Controlled Impedance
   feature (DCI) and have been locked (LOC constraint) to the I/O bank 15.
   This feature requires the VRN and VRP pins within the same I/O bank to be
   connected to reference resistors.
   The following VR pins are currently locked and can't be used to supply the
   necessary reference.
   IO Standard: Name = SSTL15_T_DCI, VREF = 0.75, VCCO = 1.50, TERM = SPLIT, DIR
   = BIDIR, DRIVE_STR = NR
   List of locked IOB's:
   	ddr3_dq<30>
   	ddr3_dq<31>
   	ddr3_dq<24>
   	ddr3_dq<32>
   	ddr3_dq<40>
   	ddr3_dq<25>
   	ddr3_dq<33>
   	ddr3_dq<41>
   	ddr3_dq<26>
   	ddr3_dq<34>
   	ddr3_dq<42>
   	ddr3_dq<27>
   	ddr3_dq<35>
   	ddr3_dq<43>
   	ddr3_dq<28>
   	ddr3_dq<36>
   	ddr3_dq<44>
   	ddr3_dq<29>
   	ddr3_dq<37>
   	ddr3_dq<45>
   	ddr3_dq<38>
   	ddr3_dq<46>
   	ddr3_dq<39>
   	ddr3_dq<47>

   List of occupied VR Sites:
   VR site AC35 is occupied by comp ddr3_dqs_p<5>
   VR site AB34 is occupied by comp ddr3_dqs_n<5>


ERROR:Place:899 - The following IOBs use the Digitally Controlled Impedance
   feature (DCI) and have been locked (LOC constraint) to the I/O bank 15.
   This feature requires the VRN and VRP pins within the same I/O bank to be
   connected to reference resistors.
   The following VR pins are currently locked and can't be used to supply the
   necessary reference.
   IO Standard: Name = DIFF_SSTL15_T_DCI, VREF = NR, VCCO = 1.50, TERM = SPLIT,
   DIR = BIDIR, DRIVE_STR = NR
   List of locked IOB's:
   	ddr3_dqs_n<3>
   	ddr3_dqs_n<4>
   	ddr3_dqs_n<5>
   	ddr3_dqs_p<3>
   	ddr3_dqs_p<4>
   	ddr3_dqs_p<5>

   List of occupied VR Sites:
   VR site AC35 is occupied by comp ddr3_dqs_p<5>
   VR site AB34 is occupied by comp ddr3_dqs_n<5>


ERROR:Place:899 - The following IOBs use the Digitally Controlled Impedance
   feature (DCI) and have been locked (LOC constraint) to the I/O bank 16.
   This feature requires the VRN and VRP pins within the same I/O bank to be
   connected to reference resistors.
   The following VR pins are currently locked and can't be used to supply the
   necessary reference.
   IO Standard: Name = SSTL15_T_DCI, VREF = 0.75, VCCO = 1.50, TERM = SPLIT, DIR
   = BIDIR, DRIVE_STR = NR
   List of locked IOB's:
   	ddr3_dq<50>
   	ddr3_dq<51>
   	ddr3_dq<52>
   	ddr3_dq<60>
   	ddr3_dq<53>
   	ddr3_dq<61>
   	ddr3_dq<54>
   	ddr3_dq<62>
   	ddr3_dq<55>
   	ddr3_dq<63>
   	ddr3_dq<48>
   	ddr3_dq<56>
   	ddr3_dq<49>
   	ddr3_dq<57>
   	ddr3_dq<58>
   	ddr3_dq<59>

   List of occupied VR Sites:
   VR site Y32 is occupied by comp ddr3_dq<62>


ERROR:Place:899 - The following IOBs use the Digitally Controlled Impedance
   feature (DCI) and have been locked (LOC constraint) to the I/O bank 16.
   This feature requires the VRN and VRP pins within the same I/O bank to be
   connected to reference resistors.
   The following VR pins are currently locked and can't be used to supply the
   necessary reference.
   IO Standard: Name = DIFF_SSTL15_T_DCI, VREF = NR, VCCO = 1.50, TERM = SPLIT,
   DIR = BIDIR, DRIVE_STR = NR
   List of locked IOB's:
   	ddr3_dqs_n<6>
   	ddr3_dqs_n<7>
   	ddr3_dqs_p<6>
   	ddr3_dqs_p<7>

   List of occupied VR Sites:
   VR site Y32 is occupied by comp ddr3_dq<62>


ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

 

What I understand is that to use several IO types on the same Bank, (which is the case, for example with bank 15, used by both the ddr3_qd's with SSTL15_T_DCI IO's and by the ddr3_dqs's with DIFF_SSTL15_T_DCI IO's) the VRN and VRP pins of this Bank must be conneted to reference resistors. But, in our case, these VR pins are used by DDR3 signal, wich generates ERRORS...

 

Am I right ?

What can I do to solve that?

 

Thank you for your help,

 

Alexandre

 

 

 

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5 Replies
gszakacs
Professor
Professor

‎02-15-2011 06:34 AM

7,149 Views
Registered: ‎08-14-2007

The kit description lists a "Free high performance  DDR3 Memory Controller."

 

Did you check to see if you received this controller.  Perhaps it uses a different

approach than the MIG core?

 

-- Gabor

-- Gabor
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jschmitz
Xilinx Employee
Xilinx Employee

‎02-15-2011 08:49 AM

7,145 Views
Registered: ‎10-23-2007

Have you looked at using DCI Cascade?  See the DCI cascade description starting on page 16 of UG361.

 

However, I agree with that you should get the design from the vendor.  The board may or may not be compatible with MIG.  The vendor is the right place to go.

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guilvard
Adventurer
Adventurer

‎02-16-2011 12:48 AM

7,107 Views
Registered: ‎03-05-2009

Yes, it was the DCI cascade !

 

Thank you !

 

The manufacturer effectively gives an example, but it is not working in impletation...

 

I now have other errors, but i will go through them.. maybe with your help again ;-)

 

Thank you,

 

Alex

 

 

 

 

 

 

 

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gdszysf
Newbie
Newbie

‎05-21-2012 05:42 AM

6,703 Views
Registered: ‎05-21-2012

@guilvard wrote:

Yes, it was the DCI cascade !

 

Thank you !

 

The manufacturer effectively gives an example, but it is not working in impletation...

 

I now have other errors, but i will go through them.. maybe with your help again ;-)

 

Thank you,

 

Alex

 

 

 

 

 

 

 

Excuse me,how did you resolved thie problem?

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cyberwizzard
Adventurer
Adventurer

‎06-17-2013 06:19 AM - edited ‎06-17-2013 06:21 AM

6,088 Views
Registered: ‎03-16-2010

This is for everyone who lands at this rather old thread after having pretty much the same error with the ML-605 board and the MIG memory controller: for some reason the cascade directives are missing in my generated MIG directives (the ncf files in 'implementation').

 

Add the following 2 lines to the 'etc/system.ucf':
CONFIG DCI_CASCADE = "36 35"; # Manual cascade for ML-605 with MIG controller - why doesnt MIG instantiate this?

CONFIG DCI_CASCADE = "26 25";

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