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Observer
Observer
15,393 Views
Registered: ‎06-24-2013

PLEASE HELP Me

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Can we convert LvCmos 2.5 i/o to Differential signalling (Lvds) inside the  Fpga ? since I want to use GTx transceivers , Transceiver only accepts differential signals ..how could i do that ??

can u please help on this one?/

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Xilinx Employee
Xilinx Employee
24,633 Views
Registered: ‎07-31-2012

Hi Sahitya,

 

From your notes i understood that you want to give some parallel input to the FPGA, store them and then output this data serially using the HSSIO transceivers inside the FPGA with an LVDS standard.

 

So how you can implement here is as per the steps below.

 

1) 1stly in your UCF you can mention the IO standard for the input signals to be LVCMOS25 (since this is your input signal standard)

2) Then you take these inputs and you can store them in the internal BRAM's.

3) Now you can connect the output of the BRAM's and give them to the GT's in the device.

4) This GT converts the parallel signals from the BRAM to serial which runs at a much higher rate(which depends on the device you use).

5) Now the GT's have an output TXP and TXN, which is how the data is outputted through the FPGA. These are the LVDS fpga outputs. You can use the coregen wizard to generate the core for the GT's which also generates the necessary UCF.

 

Please let me know if this makes it clear or you were looking for a different requirement.

 

Thanks,

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

View solution in original post

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Teacher
Teacher
15,388 Views
Registered: ‎08-14-2007

Hi,

if the fpga supports these two signal levels, why not.

It might be that you have to use different I/O banks for each signal level.

That mainly depends on the requirements for Vccaux (the power source for the I/O bank).

If both signal levels need the same Vccaux you might as well mix them on the same i/o bank.

 

The signal level for each I/O pin can be declared in the UCF file.

For LVDS outputs it might be necessary to instantiate the differential drivers separately.

Maybe you find something in the ISE  Language templates if theres also a way to infer these.

 

Have a nice synthesis

  Eilert

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Xilinx Employee
Xilinx Employee
15,382 Views
Registered: ‎07-31-2012

Hi,

 

Can you further elaborate on your query?

 

Where is the LVCMOS2.5 driver signal coming from? And how are you planning to interface these signals.

 

Becase every IO on the FPGA can be configured to difffernt IO standards based on your requirements. Every IO is paired up. one P and one N. If these are not used for differential IO's, you can use either P or N individually as an individual pin and assign it a single ended IO standard


Thanks,

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Observer
Observer
15,364 Views
Registered: ‎06-24-2013

Hi Anirudh,

 

Great...Thank you so much for reply...Here all the inputs coming to Fpga are LvCmos signals 2.5 I/o standard only ... every input signal to Fpga are LV CMOS signal only including clock signals  ...  I need to store all this LV Cmos signals in block ram, read back it and I wanted to transmit all this signals to another Fpga in very higher data rate which could be only possible through GTX Transceivers and through serial protocol to another Fpga ...here to transmit the signals at this higher rate cannot be possible through LvCmos should convert to Lvds signals ....

 

can u explain how can we convert this Lvcmossignals to Lvds signalsit ?can conversion be possible in input stage before I pass this signals to Block Ram or can conversion atleast possible at output stage ? can u please help me as soon as u see this post 

Regards 

 

Sahitya Venkatayogi

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Teacher
Teacher
15,350 Views
Registered: ‎08-14-2007

Hi,

The IOBs of the FPGA handle the level conversion.

All possible I/O levels are always converted to and from the core logic level that is used inside the FPGA.

Depending on the FPGA Family this core logic level might be 1.2V, 1.0 V or even sth. lower.

 

There's nothing to do but correctly declaring the I/O signal level in the UCF file and, in case of differential signals, using proper pin combinations for the matching _p and _n signals.

 

There is no special conversion block or HDL-statement needed.

The IO drivers of the IOBs are mostly added automatically.

Only in special cases they need instantiation, which might apply to differential signalling.

(One special case is DDR-Interfacing with IDDR2 and ODDR2 I/O-FFs)

 

But even these instantiations are basically defining the signal routing.

Level conversion is done automatically according to the UCF file settings for the pin.

 

Have a nice synthesis

  Eilert

 

 

 

 

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Observer
Observer
15,323 Views
Registered: ‎06-24-2013

Hi eilert,

 

Thank you so much for your reply ,But  there is no such documentation says that IOB element can handle level  conversion 

 

I need some thing that converts LVCmos level voltages to Lvds format so that I can transmit the data using GTX transceivers to outside the fpga

 

simply LVCMOS ---- LVDS ------ gTX TRSNCIEVR ---- OUSIDE of fpga ...... 

 

can any way is it poss??

 

please help in thjis regard

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Xilinx Employee
Xilinx Employee
15,314 Views
Registered: ‎01-03-2008

> I need some thing that converts LVCmos level voltages to Lvds format so that I can

> transmit the data using GTX transceivers to outside the fpga

 

This doesn't make sense.

 

You can have an IO input buffer that is single ended and configured for LVCMOS18, LVCMOS25, LVCMOS35.

You can have an IO output buffer that is differential and configured as LVDS, LVDS_25, LVDS_33 (depends on the family)

You can use GTX as serial multi-gigabit transceiver wth external CML inputs and outputs and internal logic for the data and control.

 

And everything inside of the device is running at a core logic level as deternined by VCCINT, because that is the way that the FPGA is designed and there is no need for anything else.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Xilinx Employee
Xilinx Employee
24,634 Views
Registered: ‎07-31-2012

Hi Sahitya,

 

From your notes i understood that you want to give some parallel input to the FPGA, store them and then output this data serially using the HSSIO transceivers inside the FPGA with an LVDS standard.

 

So how you can implement here is as per the steps below.

 

1) 1stly in your UCF you can mention the IO standard for the input signals to be LVCMOS25 (since this is your input signal standard)

2) Then you take these inputs and you can store them in the internal BRAM's.

3) Now you can connect the output of the BRAM's and give them to the GT's in the device.

4) This GT converts the parallel signals from the BRAM to serial which runs at a much higher rate(which depends on the device you use).

5) Now the GT's have an output TXP and TXN, which is how the data is outputted through the FPGA. These are the LVDS fpga outputs. You can use the coregen wizard to generate the core for the GT's which also generates the necessary UCF.

 

Please let me know if this makes it clear or you were looking for a different requirement.

 

Thanks,

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

View solution in original post

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Teacher
Teacher
15,301 Views
Registered: ‎08-14-2007

Hi,

looks like words just increase confusion in this matter.

 

Please make a sketch, beginning with a big black line in teh middle indicating the border of the FPGA.

Then depict the blocks that you need inside and outside the fpga and also the intended signal routing.

 

Have a nice synthesis

  Eilert

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Xilinx Employee
Xilinx Employee
15,249 Views
Registered: ‎07-31-2012

Hi sahitya,

 

Did you resolve your query?

 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Observer
Observer
9,503 Views
Registered: ‎06-24-2013

Hey Anirudh,

 

How are you ? I am busy in making the report till i have worked . Your solution seem to be nice,Still i have few doubts to be cleared on the thing you posted but i will came back to you from monday ..

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