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Visitor emil1985
Visitor
8,021 Views
Registered: ‎10-08-2008

Problem with IBERT

Hi.

 

I have problem using IBERT core. I'm working with Virtex5 xc5vfx70t-3ff1136 device. I want to use three MGTs(X0Y5, X0Y6, X0Y7) in IBERT core. I'm using system clock at 32 MHz and referent clock at 156.25 MHz. Target line rate is 6.25 Gbps. ChipScope detected one IBERT core and prompt message : "The user clock s not running. Cannot write to or read from IBERT core. Please reconnect the user clock and reconfigure the device". I also use IBERT with one and two MGTs with same and lower speeds but I didn't have this problem.

 

Can anybody tell me why is this happening?

 

Thanks,

Emil

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6 Replies
Xilinx Employee
Xilinx Employee
8,014 Views
Registered: ‎01-03-2008

Re: Problem with IBERT

Based on your description it sounds like either your 32 MHz clock is disabled or you assigned the clock input to the wrong pin of the device.
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Visitor emil1985
Visitor
8,009 Views
Registered: ‎10-08-2008

Re: Problem with IBERT

But designs with one or two MGTs work with same clock connected on same pin. I'm measured with scope on oscilaotr pin and clock is OK.

 

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Xilinx Employee
Xilinx Employee
8,001 Views
Registered: ‎01-03-2008

Re: Problem with IBERT

Have you verified using the PAD report file that the clock pin was correctly assigned?  Does the pin match the working designs with 1 or 2 MGTs?
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Visitor emil1985
Visitor
7,976 Views
Registered: ‎10-08-2008

Re: Problem with IBERT

This is line from .pad file :

            AH15|DCLK_IPAD<0>|IOB|IO_L5P_GC_4|INPUT|LVCMOS25*|4||||NONE||LOCATED||NO|NONE|

 

Pin assignament is same for all design, working and not working.

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Visitor sigwalt
Visitor
5,976 Views
Registered: ‎06-07-2012

Re: Problem with IBERT

you probably need to adjust user clock connections on tab 1
i.e. when using MGT X0Y0 and X0Y1 it is helpful to connect both user clocks to the X0Y1 buffer
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Voyager
Voyager
5,967 Views
Registered: ‎04-02-2011

Re: Problem with IBERT


 

I have problem using IBERT core. I'm working with Virtex5 xc5vfx70t-3ff1136 device. I want to use three MGTs(X0Y5, X0Y6, X0Y7) in IBERT core. I'm using system clock at 32 MHz and referent clock at 156.25 MHz. Target line rate is 6.25 Gbps. ChipScope detected one IBERT core and prompt message : "The user clock s not running. Cannot write to or read from IBERT core. Please reconnect the user clock and reconfigure the device". I also use IBERT with one and two MGTs with same and lower speeds but I didn't have this problem.

 

Can anybody tell me why is this happening?


 

 

Following mcgett's suggestion if your clock is ok as you verified wih osscillator.

 

is it possible for you to echange the MGT locations for working & non working and recheck it  ?

 

is the gtreset working propely of your not working MGT?

 

Or else try with sigawalt's post most probably will help in sorting out your issue.

 

 

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