07-12-2010 10:04 AM
I am a graduate student in the University of Western Ontario. I am currently working with the Virtex5 XUPV5 -LX110T FPGA development board. I coded a simple clock divider porgram in VHDL using DCM and I programmed the board with the code using IMPACT. I also set the up the appropriate ucf file for the pins I have used in the code. I have used the User clock provided in the board , divided the clock by 5 to generate a 20MHz clock , and I have assigned this output to J12 P (Diff Clock output) clock output pin.
The problem is , I am not able to get a clock output from the SMA pin J12 . I am testing the clock output on an oscilloscope, but I am not able to get any waveform from the pin. I even tested the code by designing a testbench, and I am getting the appropriate divided clock output in the simulation.
I would be grateful if somebody could help me out with this issue. I have attached the vhdl file for your reference.
07-12-2010 10:30 AM
Have you gone through all the reports, and examined all the warnings? Weret here any errors (if so you need to fix them)?
Open the .ncd in FPGA_Editor, and examine what the tools did. Check that the input you are using as a clock input is correct, and the output you are using as your differential clock output is also correct. How is the DCM reset? If you use the reset button on the board, be careful, as it is logic "0" true (the reset buttons have pullup resistors, and close to ground when pushed).
07-12-2010 08:07 PM
I did not get any errors or warnings in the synthesis report of the VHDL code, no errors or warnings in the behavioral simulation and also when I programmed the code in IMPACT.
In my VHDL, code, I programmed the GPIO buttons(North,South,East and West) to light up the LEDs (North, South,East and West) when pressed. This function works fine.
I am resetting the DCM manually using the VHDL code and I am not using the reset on the board.
I using the USER_CLK as the clock input which is a signal ended clock and I am expecting a single ended clock output from one of the differential SMA clock output pin. But when I tested the output on the oscilloscope, i just get noise.
I am not sure what could be the issue.
Anticipating your reply
07-13-2010 07:20 AM
I still am concerned that you are holding the DCM in reset. When you say that you are not using a pushbutton, and you are using the exisiing VHDL wrapper, that still needs a reset.
I also recommend you look at the design in FPGA_editor.
Finally, have you checked that the input clock is present?
07-14-2010 09:48 AM
Have you used Chipscope before? This might be a useful tool to you as you can use it to probe the ports of your DCM to find out more information on what is going on inside the fabric. As Austin said, likely there is an issue with your RESET that is causing the RESET to be held asserted. You can use the Chipscope inserter software to insert the Chipscope cores into your design and probe the reset, locked and status ports of the DCM to get an idea of what is happening to the DCM in hardware.
If you want more information on Chipscope, take a look through the users guide: