I would like to connect QDRII+ Cypress memory (cy7c1545kv18, 200 MHz) to Xilinx Virtex 5 XC5VSX95T FPGA. The MIG for Virtex 5 supports only QDRII memories.
Where can I found some information concerning QDRII+ memories and Virtex 5? I know that MIC for Virtex 6 supports QDRII+ memories. Is it possible to use somehow the code from MIC of Virtex 6 for Virtex 5 FPGA ?
I recommend you modify the Virtex-5 code to accommodate the QDR II+ changes rather than try to back port the Virtex-6 design to Virtex-5. As I recall (could be wrong), the most significant change is the latency which goes to 2.5 cycles in QDR II+. Check the datasheets carefully to see the differences. I suspect this will be the easiest route.