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Visitor sneha.lele
Visitor
6,968 Views
Registered: ‎04-05-2010

Reading data from ROM core

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I have created a ROM core using CoreGen to store a large chunk of data (65536 data values). When i instantiate the ROM in my main code, and when i give some address as input, i get the corresponding data value at the output port. So i'm sure the data is stored correctly in the ROM.

But how do i scan through the ROM? How do i access a chunk of data at a time, and not just one data value? I tried using the 'for' loop by storing data in an array, but the value stored at the last address indicated by the 'for' loop gets overwritten in all other places.

 

How do i access a big part of the ROM at a time? 

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Visitor sneha.lele
Visitor
8,952 Views
Registered: ‎04-05-2010

Re: Reading data from ROM core

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Hi,

 

I am actually sort of new to vhdl, and the only proper programming background i have is for the object oriented type. Thats where the problem lies i think!

 

I understand that i can increment the address, but how do i make sure that the address increments at every new clock cycle. This might be a very obvious step, but i don't seem to be able to figure that out. Should the 'if-else you mentioned be written in the clock process or in the stimulus process??

 

 

Sneha

 

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Teacher eilert
Teacher
6,959 Views
Registered: ‎08-14-2007

Re: Reading data from ROM core

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Hi,

The answer is : Not at all.

 

A ROM is intended to provide one word at a tome for a given address. Where the word can have different lengths, but is fixed for a certain implementation. (e.g. 8 or 16 bits etc.)

For accessing multiple adresses at the same time, there are just no wires available.

 

If the data chunks you want to access are of a constant size (e.g. 10 data words) then you could think of using 10 smaller roms, which you can access parallel.

If your application is not intended to run at maximum speed you can put your rom in another clock domain and emulate the parallel access.  Depending on the chunk size this may become difficult.

 

 

If the for loop solution would work for you everything would be all right, but I think you made some coding mistake.

From what you write I assume that you tried to run the loop in one clock cycle. That just won't work. You need N clock cycles, one for each address you are accessing in the ROM.

 

Have a nice synthesis

  Eilert

 

Visitor sneha.lele
Visitor
6,953 Views
Registered: ‎04-05-2010

Re: Reading data from ROM core

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Thanks for ur response.

I understand that a chunk of data cannot be accessed at a time. What i could do is access 1 data value at a time at every consecutive clock cycle.

But what i don't understand is how to increment the address in every cycle. Right now, in my process, i assign a particular address to the address port and i see the corresponding output at the output port. But how do i increment this address in every consecutive clock cycle, so that a new address is assigned to the address port every time and a new data value appears at the output port?

 

 

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Teacher eilert
Teacher
6,948 Views
Registered: ‎08-14-2007

Re: Reading data from ROM core

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Hi,

a simple counter can do the trick.

Either as an external component, or embedded in your controlling code.

 

 address <= address +'1';  -- with st_logic_vector types

 

This has to be inside a sequential code segment of course.

 

 You can write something like this to start accessing the rom from a given base address:

 

if load_base = '1' then

   address <=BASE_ADDRESS;

else 

  address <= address +'1';

end if;

 

Hope this helps a little.

 

Have a nice synthesis

  Eilert

 

 

 

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Teacher eilert
Teacher
6,948 Views
Registered: ‎08-14-2007

Re: Reading data from ROM core

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Hi,

a simple counter can do the trick.

Either as an external component, or embedded in your controlling code.

 

 address <= address +'1';  -- with st_logic_vector types

 

This has to be inside a sequential code segment of course.

 

 You can write something like this to start accessing the rom from a given base address:

 

if load_base = '1' then

   address <=BASE_ADDRESS;

else 

  address <= address +'1';

end if;

 

Hope this helps a little.

 

Have a nice synthesis

  Eilert

 

 

 

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Visitor sneha.lele
Visitor
8,953 Views
Registered: ‎04-05-2010

Re: Reading data from ROM core

Jump to solution

Hi,

 

I am actually sort of new to vhdl, and the only proper programming background i have is for the object oriented type. Thats where the problem lies i think!

 

I understand that i can increment the address, but how do i make sure that the address increments at every new clock cycle. This might be a very obvious step, but i don't seem to be able to figure that out. Should the 'if-else you mentioned be written in the clock process or in the stimulus process??

 

 

Sneha

 

View solution in original post

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Teacher eilert
Teacher
6,905 Views
Registered: ‎08-14-2007

Re: Reading data from ROM core

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Hi Sneha,

Ah, I see, so welcome to the world of hardware design. :-)

 

Things are different here, because everything you describe (not programm!) turns out to become some real silicon.

So what we are dealing with are combinatorical stuff (AND, OR, +,-, compare and multiplex etc.) and flipflops.

The flipflops are clocked and store values, but besides just storing they also serve as time quantisation elements, giving us the oportunity to do things sequential (with feedback and everything).

 

To make the design process more structured, we mostly follow the paradigm of "synchronous design".

So, whatever you design will mainly look like this:

 

process (reset,clock) is

 begin

  if reset = '1' then

    --initialize some values here

  elsif rising_edge(clock) then -- this becomes clock dependend and all signals are stored in ffs

    -- do some logic or arithmetic stuff here

  end if;

end process;

 

You should learn about the difference between signals and variables, and how loops behave in a clocked process compared to a combinatorical process.

I recently found a good book that explains the concepts and also goes into design details beyond just explainig the syntax of VHDL:

"RTL Hardware Design Using VHDL" by Pong P. Chu

 

Maybe some reading will save you a lot of time.

 

Have a nice synthesis

  Eilert

 

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