12-02-2012 11:33 AM - edited 12-02-2012 11:36 AM
i am using a virtex 5 fpga xc5vsx50t-1 (ISE 10.1) and i had some questions reg. the PLLs for this family.
i guess PLLs are mainly used to change the o/p freq ... get multiple clocks with varying freq and phase etc.
i read onlne and there is a pll_drp core which mates with the pll_adv core to dynamically change the o/p frequency, as per some address/control signals. however, in the ip core gen / xilinx arch wiz option for ISE 10.1, i was not able to find the pll_drp or the pll_adv.
so i wanted to know if these cores are available for the V5 family that I am using. and if so, which IP core option would have them? which one should i use? the closest I can see is the "dynamically switch between clocks PLL 9.1i" core but in the gen, it does not give an option to take in any control signals to swithc between the clocks or dynamically change the o/p freq ...
The clocking IP cores that I have for my fpga are as in the screenshot.
12-02-2012 03:34 PM
What you are looking at here is are the IP cores that can be generated by the various wizards in ISE. These all generate interconnections of existing hardware blocks inside the FPGA - they are "helpers" for creating some of the more common clocking circuits.
Some of these use the Virtex-5 PLL. The PLL is a quite complex block that has LOTS of functionality. Some of the functionality (like the dynamic reconfiguration port - DRP) is very advanced stuff, and is only used in very rare cases. As a result, Xilinx offers different "primitives" that expose more or less of the underlying complexity of the PLL.
The simpler primitive "PLL_BASE" exposes only the basic functionality of the PLL - this is sufficient for most applications. The more complete primitive "PLL_ADV" exposes ll the functionality of the PLL, including the DRP ports.
If you want to use the DRP of the PLL, you will not be able to access them from the "New Source Wizards" - you will have to manually instantiate the PLL_ADV primitive yourself, including connecting up the (approximately) 28 ports and setting correct values for the (approximately) 40 parameters. You can find the complete list in UG190 (the Virtex-5 data sheet).
Now the warning. Using the DRP is NOT simple - it requires a lot of understanding of the underlying structure of the PLL and the registers that exist in them. Also, note that you cannot transition between different frequencies "seamlessly" - on each change, the PLL will need to be reset, and will need to re-lock (which takes many many clock cycles...) That being said, UG190 points you to UG191 which has some details (at least on changing the M & D).