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Explorer
Explorer
6,192 Views
Registered: ‎08-23-2011

Reg: toggling GPIO pins of V5 XC5VSC50TFF1136 at high frequency ...

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hi,

 

i am using the xilinx virtex5 XC5VSC50TFF1136 with a speed grade of -1, (xilinx ise 10.1)

 

i am using a local 100 MHz osc. to clock it. What I am trying to do is bring out the 100 MHz clock on a GPIO pin and then see it on the oscillosope. The problem i am facing is that when i check the signal of the GPIO pin on the oscilloscope, i dont see a clean square wave but a triangular wave at high frequencies. however, when i decrease the speed of the output signal (divide the clock and then send it to the GPIO) , then around 3 - 4 MHz, i get a proper square wave on the oscilloscope.

 

i was wondering if this is a problem with the GPIO pin or if its just a limitation of the FPGA device (they cant toggle a GPIO pin that fast)? Or should i be using some specific constraint in the UCF file to get a clean square wave on the GPIO pin at high freq? I've used slew = fast but it seems to have no effect. I have verified and the osc. is running @100 MHz.

 

please do let me know ...

 

thanks,

z.

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Xilinx Employee
Xilinx Employee
8,102 Views
Registered: ‎01-03-2008

Re: Reg: toggling GPIO pins of V5 XC5VSC50TFF1136 at high frequency ...

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> My scope is rated upto 60MHz, with a 20MHz BW limit

 

Your scope simply isn't good enough to observe a 100 MHz (or a 50 MHz) waveform.  If you use a better scope the results will be as good as you see with lower frequency signals with this scope.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

View solution in original post

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4 Replies
Instructor
Instructor
6,190 Views
Registered: ‎07-21-2009

Re: Reg: toggling GPIO pins of V5 XC5VSC50TFF1136 at high frequency ...

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If you want to see nice, clean square edges, you will need a scope (and probes) rated for (at least) 350MHz bandwidth.

 

  • How fast is your scope and your probes?  Post scope traces, with no more than 2 clock cycles filling the screen
  • What IOSTANDARD and what output drive level are you using for the clock output?
  • Are you properly grounding your 'scope probes when you probe the clock signal?
  • Is your scope set for 1M-ohm probes or 50-ohm input?
  • Is the scope's BANDWIDTH LIMIT setting enabled?
  • Can you probe the 100MHz oscillator input to the FPGA?  Does this waveform look the same as the FPGA output?

 

-- Bob Elkind

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Explorer
Explorer
6,160 Views
Registered: ‎08-23-2011

Re: Reg: toggling GPIO pins of V5 XC5VSC50TFF1136 at high frequency ...

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Hi,

 

Sorry for the late reply.

 

My scope is rated upto 60MHz, with a 20MHz BW limit, but the BW limit is set to off by me.

The probles are set for 200MHz

 

The UCF file constraint I am using for the output is - IOSTANDARD = LVTTL | DRIVE = 16 | SLEW = FAST;

 

Even if I try to see a 50MHz output, its more triangular. But at lower frequencies, I do get a proper o/p. 

 

When I add a 50ohm load to the probe, the waveforms still look triangular. 

 

Any ideas on what I can change on the probe/oscilloscope or the UCF file ? Help will be greately appreciated ...

 

Thanks.

Zubin.

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Xilinx Employee
Xilinx Employee
8,103 Views
Registered: ‎01-03-2008

Re: Reg: toggling GPIO pins of V5 XC5VSC50TFF1136 at high frequency ...

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> My scope is rated upto 60MHz, with a 20MHz BW limit

 

Your scope simply isn't good enough to observe a 100 MHz (or a 50 MHz) waveform.  If you use a better scope the results will be as good as you see with lower frequency signals with this scope.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

View solution in original post

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Teacher rcingham
Teacher
6,146 Views
Registered: ‎09-09-2010

Re: Reg: toggling GPIO pins of V5 XC5VSC50TFF1136 at high frequency ...

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"My scope is rated upto 60MHz"

Are there test equipment hire companies in your locality?

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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