03-14-2009 06:52 AM
Im currently trying to implement a 16:1 serialization circuit using the OSERDES. However i found that the maximum serialization i can go is 10:1 using DDR master and slave mode. How can I go up to 16:1 using the OSERDES available? Any help will be greatly appreciated. Thank you.
03-17-2009 05:14 AM
Jeremy,
Your figure is exactly what I mean.
Following hints:
- The input register of the OSERDES does not have an enable. It is alwasy enabled.
- The enable of the OSERDES is connected to teh last registers of the serializer. Using the enabl stops the output but everything else keep s going on.
- Data is loaded into the OSERDES at a rising edge of CLKDIV.
- Data is transferred from the parallel register to the parallel-to-serial register when the number of bits given in DATA_WIDTH is reached.
- It is thus possible to load parallel data in the OSERDES before all data is shifted out.
- In you case, conduct the data mux with the CLKDIV clock (logic).
Cheers,
Marc
03-16-2009 12:14 AM
Hi,
Split your 16 bits in two times 8-bit.
Double the 16-bit clock or divide the serial clock.
Kind regards,
Marc
03-16-2009 09:45 AM
Hi Defossez,
Thank you for your prompt reply. I give your suggestion a thought and drew the attached picture. Do you mean that way? Or did i get you wrong?
03-17-2009 05:14 AM
Jeremy,
Your figure is exactly what I mean.
Following hints:
- The input register of the OSERDES does not have an enable. It is alwasy enabled.
- The enable of the OSERDES is connected to teh last registers of the serializer. Using the enabl stops the output but everything else keep s going on.
- Data is loaded into the OSERDES at a rising edge of CLKDIV.
- Data is transferred from the parallel register to the parallel-to-serial register when the number of bits given in DATA_WIDTH is reached.
- It is thus possible to load parallel data in the OSERDES before all data is shifted out.
- In you case, conduct the data mux with the CLKDIV clock (logic).
Cheers,
Marc
03-17-2009 07:02 AM
03-18-2009 05:38 AM
Hi,
I had te be somewhat more clear in my answer.
What I meant is that you should use the CLKDIV clock and some logic to get the multiplexer switching.
And, you did exactly that, use the CLKDIV and divide it by two to get the multiplexer switching.
Regards,
Marc
03-18-2009 06:01 PM