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jeremylbt
Newbie
Newbie
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Registered: ‎03-14-2009

Regarding the use of Xilinx OSERDES

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Im currently trying to implement a 16:1 serialization circuit using the OSERDES. However i found that the maximum serialization i can go is 10:1 using DDR master and slave mode. How can I go up to 16:1 using the OSERDES available? Any help will be greatly appreciated. Thank you.

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defossez
Xilinx Employee
Xilinx Employee
12,223 Views
Registered: ‎04-17-2008

Jeremy,

 

Your figure is exactly what I mean.

Following hints:

- The input register of the OSERDES does not have an enable. It is alwasy enabled.

- The enable of the OSERDES is connected to teh last registers of the serializer. Using the enabl stops the output but everything else keep s going on.

- Data is loaded into the OSERDES at a rising edge of CLKDIV.

- Data is transferred from the parallel register to the parallel-to-serial register when the number of bits given in DATA_WIDTH is reached.

-     It is thus possible to load parallel data in the OSERDES before all data is shifted out.

-     In you case, conduct the data mux with the CLKDIV clock (logic).

 

Cheers,

 

Marc

 

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defossez
Xilinx Employee
Xilinx Employee
10,019 Views
Registered: ‎04-17-2008

Hi,

 

Split your 16 bits in two times 8-bit.

Double the 16-bit clock or divide the serial clock.

 

Kind regards,

 

Marc

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jeremylbt
Newbie
Newbie
10,001 Views
Registered: ‎03-14-2009

Hi Defossez,

 

Thank you for your prompt reply. I give your suggestion a thought and drew the attached picture. Do you mean that way? Or did i get you wrong?

 

http://img10.imageshack.us/img10/9907/161interface2.jpg

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defossez
Xilinx Employee
Xilinx Employee
12,224 Views
Registered: ‎04-17-2008

Jeremy,

 

Your figure is exactly what I mean.

Following hints:

- The input register of the OSERDES does not have an enable. It is alwasy enabled.

- The enable of the OSERDES is connected to teh last registers of the serializer. Using the enabl stops the output but everything else keep s going on.

- Data is loaded into the OSERDES at a rising edge of CLKDIV.

- Data is transferred from the parallel register to the parallel-to-serial register when the number of bits given in DATA_WIDTH is reached.

-     It is thus possible to load parallel data in the OSERDES before all data is shifted out.

-     In you case, conduct the data mux with the CLKDIV clock (logic).

 

Cheers,

 

Marc

 

View solution in original post

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jeremylbt
Newbie
Newbie
9,962 Views
Registered: ‎03-14-2009
Hi,

Thank you once again. I've implemented the 16:1 serializer successfully. However I don't really see how the design can work using "CLKDIV" as the data mux clocking. I'm now using the a "CLKDIV/2" derived clock to mux my data input and it works.

Regards
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defossez
Xilinx Employee
Xilinx Employee
9,934 Views
Registered: ‎04-17-2008

Hi,

 

I had te be somewhat more clear in my answer.

        What I meant is that you should use the CLKDIV clock and some logic to get the multiplexer switching.

And, you did exactly that, use the CLKDIV and divide it by two to get the multiplexer switching.

 

Regards,

 

Marc

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jeremylbt
Newbie
Newbie
9,912 Views
Registered: ‎03-14-2009
Hihi,

One last question. How do i forward a 622.08Mhz output clock (in phase with my DDR data output) to my external serialization chip. I tried to generate a 622.08Mhz clock using DCM but it's not within the frequency specs of the DCM. I've generated the following clocks for my design using the DCM.

1) 80Mhz
2) 40Mhz
3) 320Mhz

Thank you for your help.
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