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bonita.h
Adventurer
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Registered: ‎12-01-2010

Relization of Low frequency, dual_signal with fixed phase shift?

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Hi,

   I tried to use DCM to generate a couple of signals, where one signal has a fixed phase shift with the other one.

   My idea was this:

   Using one signal as the input of CLKIN, and get another signal from CLKDV or CLKFX. Therefore, I could get the phase shift by setting "PHASE SHIFT" value. However, the frequencies of the two signals should respectively be 6MHz (CLKIN) and 3MHz (CLKDV). In low frequency, CLKIN can reach to as low as 1MHZ, but the output must be CLKFX or CLKFX180. But CLKFX or 180 cannot be lower than 32MHZ.

    I don't know how to solve this problem, can anyone give me any hint to do it? Can I use two DCM working parallelly , one generates 6MHZ and one generate 3MHZ with a fixed and adjustable phase shift?

 

   Thanks very much!

 

   Eric

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eteam00
Instructor
Instructor
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Registered: ‎07-21-2009

Controlling a 96MHz state machine gives you 16 discrete phases of a 6MHz clock, right?  (think of a johnson counter).

 

Phase shifting the 96MHz output of the DCM should give you another factor of 256 granularity, for a total of 4096-phase resolution.

 

-- Bob Elkind

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eteam00
Instructor
Instructor
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Registered: ‎07-21-2009

Generate a 16x clock (96MHz), and build a state machine to generate the 6MHz and 3MHz clocks you desire.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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bonita.h
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Registered: ‎12-01-2010

Hi, Bob,

 

   Can you please give me  futher explanation about how to adjust the phase shift using statemahcine?

 

   The phase shift step should be as small as possible in my work. That's why I want to use DCM to do it since the phase shift value can be 1/256 of CLKIN period. If I use state machine, can I get such a small step?

 

    Thanks!

 

    Eric

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eteam00
Instructor
Instructor
9,549 Views
Registered: ‎07-21-2009

Controlling a 96MHz state machine gives you 16 discrete phases of a 6MHz clock, right?  (think of a johnson counter).

 

Phase shifting the 96MHz output of the DCM should give you another factor of 256 granularity, for a total of 4096-phase resolution.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

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bonita.h
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Registered: ‎12-01-2010

 

 

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bonita.h
Adventurer
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Registered: ‎12-01-2010

dual_clock.jpg

Hi, Bob,

    This is what I want to use in my design. In the low frequency mode, only DFS output (clkfx and clkfx180) can be used. So I cannot use clk0 as the feedback. I connect the output (6MHz) of FSM to CLKFB. I am not sure this can help me to get a stable phase relationship between the signal of 6Mhz and the signal of 3MHz, because the normal feedback CLK0 has the same frequency as CLKIN. But here, i am using a different frequency as the feedback .

     Can you please give me a guidance?

     

   Best regards,

   Eric

 

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eteam00
Instructor
Instructor
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Registered: ‎07-21-2009

Can you please give me a guidance?

 

Do you want 6MHz and 3MHz outputs to track one another?  If YES, then FSM should generate both clocks, agreed?

Which FPGA family are you targeting?

 

FSM is used to propagate phase offset and provide additional phase offset.  Using the resulting clock as the feedback to the DCM would result in 'nulling' the phase offset.  You should re-read the documentation on the functions of the DCM.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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bonita.h
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Registered: ‎12-01-2010

Hi, Bob,

 

I am targeting Virtex 5.

Yes, one tracks the other one with stable and adjustable phaseshift.

But, If one FSM generates both clocks, how can I get  a high phaseshift resolution ?

 

Regards,

 

Eric

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eteam00
Instructor
Instructor
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Registered: ‎07-21-2009

But, If one FSM generates both clocks, how can I get  a high phaseshift resolution ?

 

This is a good time for you to summarise what your design is intended to accomplish.

 

Input is 33MHz clock, yes?

Output is 6MHz clock and 3MHz clock.  Please describe these clocks with more detail.

 

  • timing relationships between 6MHz and 3MHz clocks
  • timing relationships between 6MHz and 33MHz clocks
  • timing relationships between 3MHz and 33MHz clocks

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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bonita.h
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Registered: ‎12-01-2010

Yes, Bob, as you said, input 33MHz and dual outputs are 6Mhz and 3Mhz (actually, the outputs can be any frequency pairs where one frequency is a double of the other one, normally below 10Mhz. Only in this example, I set them as 6 and 3Mhz respectively) .

 

  • timing relationships between 6MHz and 3MHz clocks      (Important=>stable and adjustable phaseshift, resolution the higher the better)
  • timing relationships between 6MHz and 33MHz clocks    (not important)
  • timing relationships between 3MHz and 33MHz clocks    (not important)

If two clock are all from FSM, the phase-shift merit of DCM can not be used, I think. .

 

Regards,

Eric, 

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