10-10-2012 03:12 AM
I want to power down the Virtex-6 without powering down the DDR3 chips and losing their content.
Mainstream DDR3 chip MT41J128M8XX-15E, which is also officially supported by Virtex-6 Memory Controller Core (according to the user guide), has an automatic self refresh function, so that the memory controller can be shutdown to save power without losing the data stored on the DDR3 devices also no external clocking is needed.
Page-104 and 162 of http://download.micron.com/pdf/datasheets/dram/ddr3/1Gb_DDR3_SDRAM.pdf
Is it practically possible to use this feature (apparently targets my purpose) while Virtex-6 being the memory controller device? If it is possible, what are the tricks concerning the implementation? Has anyone tried it?
Even if this feature is not supported by V6-MIG (I could not find any clue within the related user guides and datasheets), would you recomend trying a custom workaround solution?
Is it somehow possible keeping the CKE low during normal refresh operation for issuing a manual self-refresh command? (It seems to be the only requirement for the self refresh command)
Would turning the FPGA (so the memory controller block) off and on corrupt the data stored on DDR3 devices, even if I am able to keep the supply rails of the DDR3 devices stable enough?
I would appreciate any help very much.
10-10-2012 09:57 AM
Sounds pretty tricky to do (make it work). The FPGA devcie powers on with all IO tristate, but when the power is removed from an IO bank, the Vcco collapses to near 0volts, perhaps pulling all the IO down to ground (because the intrinsic IO protection diodes are always present).
One would have to modify the memory interface controller, so that it doesn't wake up and trash the memories, as well.