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Observer phalpern
Observer
2,194 Views
Registered: ‎05-26-2011

Unused ports on DSP48E1

Hello.  In the Virtex-6 DSP user guide (UG369, v1.3), note 3 for the ports listing in Table 2 says that if ports A through D are not being used, to configure them in a certain way to reduce power.  One of the recommendations is to set attribute A/B/C/DREG to 1. No problem, I did that.

 

However, when I simulate my design, I get a "DRC Warning:  Since D port is not used, please set DREG to 0 to save power."

 

So the UG says set it to 1, the simulation file implies it should be 0.  Anyone know which is correct?

 

Thx much.

1 Reply
Xilinx Employee
Xilinx Employee
2,175 Views
Registered: ‎11-28-2007

Re: Unused ports on DSP48E1

The UG is correct. When the D port is not used, set DREG=1 and CED=0 and RSTD=0 to save power. A change request has been filed against the simulation model.

 

 


@phalpern wrote:

Hello.  In the Virtex-6 DSP user guide (UG369, v1.3), note 3 for the ports listing in Table 2 says that if ports A through D are not being used, to configure them in a certain way to reduce power.  One of the recommendations is to set attribute A/B/C/DREG to 1. No problem, I did that.

 

However, when I simulate my design, I get a "DRC Warning:  Since D port is not used, please set DREG to 0 to save power."

 

So the UG says set it to 1, the simulation file implies it should be 0.  Anyone know which is correct?

 

Thx much.


 

Cheers,
Jim