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Voyager
Voyager
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Registered: ‎02-17-2009

V4 DSP48 Clock to out from P register to P output timing

Hi all,

 

This is a repost from comp.arch.fpga. 


I am using a 48-bit accumulator reference design from the XtremeDSP for
Virtex-4 User's Guide (UG073). The static timing analysis tool assigns very
long clock to out time for the output of this block - 2.361 ns for the 10
speed grade in V4FX60. Looking at the datasheet this time is more in line
with the clock to out time from M register to P output. However, the M
register is not used in the design and the P-register is present... The time
analyzer designates this time as Tdspdck_opp while in the datasheet there
are Tdspcko_pp and Tdspcko_pm... The former is much lower than what is being
reported by the analyzer, and the latter is slightly bigger... Could someone
shed some light on this?

 

The source file name is accum48.vhd and it is available from the link below:
http://www.xilinx.com/support/documentation/user_guides/ug073_c02.zip

Thanks,
/Mikhail

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