05-26-2014 04:01 AM
I have a specific question about the function of the VRN/VRP resistors. Can I consider them really as a parallel termination resistors which are connected internally from each pin to VCCO and GND of the corresponding bank or is it somehow internally fixed conneted to VCCO/2?
On page 27 in UG471 Fig.1-11 you can find an illustration which shows there is an separated termination (VCCO/GND) but when I change the resistor values to e.g. VRN/VRP = 75/150 ohms then the parallel termination voltage stays at VCCO/2.
It would be interesting why this behaves like this and is there any way to change them (also VREF) to other values than VCCO/2?
05-26-2014 04:14 AM - edited 05-26-2014 04:27 AM
What is your application?
VRP and VRN are mainly used for memory applications and need to be conected to VTT
If you look at SSTL or HSTL VTT = VCCO/2, hence the figures show VCCO/2.
Also VRN and VRP or VREF are needed for Specific IO standards the details of which can be found in UG471 and all of them need to have them connected to VTT(VCCO/2)
Please also refer table "VCCO and VREF Requirements for Each Supported I/O Standard"
05-26-2014 04:26 AM
yes, but externally they are connected to VCCO/GND which is the same as VTT. But anyway, I need to have a circuitry which has no symmetrical output swing margin like it does with standard SSTL. VTT should be more like 2/3 VCCO and therefore I need to change VRP/VRN values. Since I don't know the internal behavior of the IOBs of the V7 regarding DCI I thought it might be helpful to ask.
05-26-2014 04:43 AM
So in your case what is VCCO and IOstandard of the signals ?
To avail DCI benifits I think you need to have one of the DCI I/O standards, please refer "XILINX DCI" section -page 20 in UG471
05-26-2014 08:11 AM
05-26-2014 10:33 PM - edited 05-26-2014 10:38 PM
Hope you are trying to derive POD IOstabdard with existing IOstandards in 7 series by manupulating VRP and VRN values.
But Xilinx has evaluated VRP and VRN values and the termination voltages as specified in UG471, so other than VCCO/2 is something that we cannot comment, haven't seeapplications of this type, so you might need to work out with IBIS simulations.
POD IO standard is supported in Ultrascale device only
Hope this clarifies
05-27-2014 12:30 AM
thanks for your answers. All the things are already written in the data sheet I know. But I thought it might be a good way to get the POD a bit closer, of course not with maximum speed but at least that dc/ac levels and signal waveform are more correct. Anyway, I tried simulations and it actually looked quite alright. But real lab measurements show something different. A good thing would to know what's going on inside the V7 when calibrating on the these resistors. It seems that is not just a simple mirroring of the values which appear on the IOBs. It seems far more complicated.
That POD is available on the Ultrascale only I know already. This is actually the point why I am doing this here.
05-27-2014 01:15 AM
05-27-2014 03:24 AM
Hello to all thank you to all so far, and very special thanks to robinliuy. This was actually the answer I was waiting for and this should help me to get on. I will get back if I know more on this.
05-29-2014 05:49 PM
@mriedel "Can I consider them really as a parallel termination resistors which are connected internally from each pin to VCCO and GND of the corresponding bank"
In past Virtex generations, VRP/VRN are connected to a dynamic circuit which cycles though the various IO standards and coarse/fine internal DCI adjustment tap settings to calibrate the termination values.
I have not looked into how this works in recent families, but below are some older Answer Records describing this VRP/VRN calibration operation; the figure of #12573 particularly illustrates the Virtex-2 VRP/VRN stepping cycle.
Also note that the FreezeDCI issues mentioned in these Answer Records are handled differently in newer parts.
AR# 12573 Virtex-II/Virtex-II Pro - DCI is not working as I expected. How do I debug this? (XCITE)
AR# 13012 5.1i Virtex-II/Virtex-II Pro BitGen - Can I turn off the DCI clock after configuration? (AM issue patch, FreezeDCI)
AR# 11814 Virtex-II/Pro DCI - What is the error tolerance of DCI? Does it change if I use the FreezeDCI patch?
AR# 31634 Virtex-II/Virtex-4/Virtex-5 - The DCI calibration action is NOT modeled in HSPICE I/O models