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melinda3
Visitor
Visitor
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Registered: ‎11-11-2009

Verilog - Single Port Block RAM with registered output

Hi,

 

I need single port block RAM with registered output. I use Verilog HDL...(Virtex-5). I change XST Template Verilog code for single port BRAM:

//// Single-Port RAM with Synchronous Read (Read Through)//module v_rams_07 (clk, we, a, di, do);input clk;input we;input [5:0] a;input [15:0] di;output [15:0] do;reg [15:0] ram [63:0];reg [5:0] read_a;always @(posedge clk) begin if (we) ram[a] <= di; read_a <= a;endassign do = ram[read_a];endmodule

 to:

 

module v_rams_07 (clk, we, a, di, do);input clk;input we;input [5:0] a;input [15:0] di;output reg [15:0] do;reg [15:0] ram [63:0];reg [5:0] read_a;always @(posedge clk) begin if (we) ram[a] <= di; read_a <= a; do <= ram[read_a];endendmodule

 

 ,but with this modification, XST inffers dual port block BRAM instead single port BRAM.

 

 

 

How to inffer single port BRAM with registered output? Am I doing something wrong?

 

(PS: I saw in CoreGen we can add this options - registered output, but I need/wanna to inffer that BRAM design) 

 

Best Regards 

 

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ywu
Xilinx Employee
Xilinx Employee
14,697 Views
Registered: ‎11-28-2007

Try registering the output of the ram instead of the registering the address input.

 

 

Cheers,

Jim

 

Cheers,
Jim
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melinda3
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Registered: ‎11-11-2009

Hi,

 

Do you mean just to delete line : read_a <= a; and write do <= ram[a];  ?

 

Best Regards

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melinda3
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Registered: ‎11-11-2009

Hi again,

 

(*) Just to add remark to my previous question ...I read that for Virtex-5 Block RAM - "All inputs, data, address, clock enables, and write enables are registered".

 

1)Can someone explain me on XST template example I wrote in my first post, why then in this example "Single-Port RAM With Synchronous Read (Read Through)"  we have read address  registered - inplicitly, if all inputs are automatically registered? Please clear this ....

 

2)Does (*) mean that "Single-Port RAM With Synchronous Read (Read Through)" have all inputs registered also we didn't write inplicitly that all inputs are also regs or ....?

 

 

 Thanks and best regards

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ywu
Xilinx Employee
Xilinx Employee
14,673 Views
Registered: ‎11-28-2007

Yes. and also add one more register after do before sending it to the output (see below where I added an intermediate register do0). Please also note that xst infers distributed RAM or BRAM based on the size. For small RAMs, you may need to use ram_style constraint to fore the use of BRAM.

 

module v_rams_07 (clk, we, a, di, do);

input clk;
input we;
input [6:0] a;
input [15:0] di;
output reg [15:0] do;

reg [15:0] ram [0:127];
reg [15:0] do0;

reg [5:0] read_a;

always @(posedge clk) begin 
if (we)    ram[a] <= di; 

do0 <= ram[a];

do <= do0;
end

endmodule

 


melinda3 wrote:

Hi,

 

Do you mean just to delete line : read_a <= a; and write do <= ram[a];  ?

 

Best Regards


 

 

Cheers,
Jim
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ywu
Xilinx Employee
Xilinx Employee
14,672 Views
Registered: ‎11-28-2007

1) It's just a coding style. You either register the address input or register the ram output to reflect the one cycle latency of the RAM. When it comes to inference it's all about the coding style. Stick to templates that work, you will be fine.
Cheers,
Jim
 

melinda3 wrote:

Hi again,

 

(*) Just to add remark to my previous question ...I read that for Virtex-5 Block RAM - "All inputs, data, address, clock enables, and write enables are registered".

 

1)Can someone explain me on XST template example I wrote in my first post, why then in this example "Single-Port RAM With Synchronous Read (Read Through)"  we have read address  registered - inplicitly, if all inputs are automatically registered? Please clear this ....

 

2)Does (*) mean that "Single-Port RAM With Synchronous Read (Read Through)" have all inputs registered also we didn't write inplicitly that all inputs are also regs or ....?

 

 

 Thanks and best regards


 

Cheers,
Jim
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