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Newbie arasut
Newbie
2,157 Views
Registered: ‎04-12-2010

Virtex-4 VP_SM pin connections.

Hi,

 I am using ML401/ML402/ML403 evaluation platform and in the document ‘Virtex-4 FPGA Packaging and Pinout Specification’ (UG075), Page Number: 46, it says, Pins, VP_SM, VN_SM, VREFN_SM, VREFP_SM, AVDD_SM and AVSS_SM should be connected to GND. But in the associated schematic diagram(ML401_2_3.pdf), these pins are connected via resistors and capacitors. What is the purpose of these pins?

How are they used in this schematic?

 

Regards,

Arasu
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Xilinx Employee
Xilinx Employee
2,138 Views
Registered: ‎01-03-2008

Re: Virtex-4 VP_SM pin connections.

The ML40x boards were developed in the early ES phase of the Virtex-5 family product life.  When these devices went to production a feature called System Monitor was removed and the documentation updated to reflect this.

http://www.xilinx.com/support/answers/20102.htm

 

Follow the the recommendations in ug075 and not the ML40x schematics 

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