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Visitor richardnock
Visitor
4,329 Views
Registered: ‎08-26-2009

Virtex 4 idelay

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Hi All,

 

I have recently migrated to Xilinx from another vender. My top level design is a schematic (ISE 10.1) and I have used the clocking wizard to take a 50 MHz clock and multipluy it up to 200MHz for the idelayctrl.

 

All I want is fixed delay idelay's to create a tapped delay line, i.e one signal in to each I pin, and delayed verions of itself going to test points for now (soon to go to latches upon observing the linearity of the line). Problems are arising on the inputs of the idelays, giving rise to:

 

* errors than an output was connected to output (i pin of the idelay), although that problem is now solved. :)

* The following error :FATAL_ERROR:Pack:pktv4iob.c:1015:1.43 - Input buffer INPUTDEL_IBUF drives multiple
   DELAYCHAIN symbols.  The implementation tools can not pack the design. 
   Process will terminate. For technical support on this issue, please open a
   WebCase with this project attached at http://www.xilinx.com/support.

 

 

I have set the type to fixed, and tied all pins bar I (and O of course :) ) to ground.

 

Does anyone have any guidance on this? Also is there anyway to attach the I pin to the internal fabric? It would make life so much easier then, I could use the clock divided down for testing. When I tie multiple I pins together i get the aformementioned error or unrouteable nets.

 

I know I could delay my clocks with a DCM (shift  phase) but I would like to try both approaches to oversampling. Pulling my hair out with this ;)

 

Any help appreciated :D
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Visitor richardnock
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5,241 Views
Registered: ‎08-26-2009

Re: Virtex 4 idelay

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Problem solved for anyone that is interested.


You can use IOBUF elements to effectively share a signal to numerous IBUF's. Set the T pin low and use the read pin to feed each idelay.

 

 

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Visitor richardnock
Visitor
5,242 Views
Registered: ‎08-26-2009

Re: Virtex 4 idelay

Jump to solution

Problem solved for anyone that is interested.


You can use IOBUF elements to effectively share a signal to numerous IBUF's. Set the T pin low and use the read pin to feed each idelay.

 

 

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