05-09-2011 06:48 AM
I'm connecting an HSTL RAM output to a Virtex-6 HSTL_I_DCI input.
I'm modelling this in Hyperlynx., but the resultant received signal looks pretty bad (overshoot, rininging etc). When I add parallel termination resistors (as shown in Figure 1-33 of UG361, v1.3) it looks as I'd expect. I thought the HSTL_I_DCI would automatically use the 100 Ohm parallel resistor termination. Are these resistors not in the ibis model or do I need to modify this file to use them?
When I choose the virtex6.ibs model I can select the various I/O standards, but not explicitly the pull-ups/ downs. How do I know if I'll need to add external resistors (which I don't think I'll need, but l'd like the analysis to support this)?.
05-09-2011 09:00 AM
At times, the IBIS and DCI just don't seem to want to understand each other...or in other words, the IBIS simulation of the DCI with termination acts as if there is no termination at all (I have seen this myself from time to time).
That said, I added the termination as a resistor to the simulation in Hyperlynx. i think the same problem also exists in teh spice models (which are the source of the IBIS models at Xilinx).
Reason being that running a spice simulation until the DCI is converged would take perhaps a few days, and there just isn't time to run the simulations for that long (DCI has a state machine, a serial comm bus, feedback system, and so on). Not sure if you did run the simulation until convergence, it could extract a valid IBIS model.
I think that we then add the resistor to the IBIS model, by hand edit. This was probably missed for this standard...
Bottom line: when you don't see the termination, add it as a fixed resistor. Report it as a bug.
03-09-2012 11:50 AM
I'm using the SSTL15_DCI_I IBIS model in the generic virtex6.ibs v1.8. It appears (based on sim differences with the SSTL15 model) that the *_DCI_I version of the model is accounting for the Thevenin termination. However, due to trace impedances that are lower than 50 ohms, I'd like to change the value of the DCI resistors / Thevenin termination to optimize the termination. Is it possible to do this using the IBIS models? If so, how?
I'm guessing that just using the SSTL15 model with manual resistors added is the only option?
03-16-2012 02:32 AM
I would urge you to open a webcase and we can see if this is a genuine bug in the models and attemp to get it fixed.
04-09-2012 02:20 PM
I am also looking at the SSTL15 and DCI models at the moment.
The issue I am seeing is that the drive voltage is not very high. When I do a termination analysis in Hyperlynx it says that the driver impedance is unusually high (17 ohms iirc).
Looking at the IBIS model itself, on the rising waveform it never gets to be higher than 1.3140V for the typical case.
Either or both of these may well be the source of the issue, but essentially what I am seeing in the silumation is under driven signals that don't cleanly clear the input thresholds for the DDR3.
Basically each address line is driving 4 DDR3 ICs and then terminated to VTT - though now that I mention this, am wondering if I have issues in the termination level...!