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Anonymous
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Virtex 6 ESD damage

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I've had a board with an LX75T returned to me due to a major fault. The board takes excess current, won't power up and the FPGA gets very hot. The Vccaux rail (supplied by a 3A LDO) is unable to reach 2.5V, presumably due to over-current limit. The Vccint rail is OK at 1.0V.

 

Further investigation (with the board powered off) of the I/O lines which are easily accessible at an external connector (around 100 from 3 banks) shows that nearly all read approx. 50K resistance to GND. However 3 read 2.9 Ohms, 1 reads 1.7K and another 206 Ohms.

 

Could this be the result of some kind of ESD event at these I/O pins? Both the Vcco and Vccaux read approx. 0.6 Ohms to GND although it's sometimes hard to get a meaningful reading with power rails with lots of capacitance but does fit the evidence as I see it.

 

I've never had an FPGA fail before. Is this kind of behaviour indicative of a distructive ESD event does anyone know?

 

Thanks,

 

Rog.

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Scholar
Scholar
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Registered: ‎02-27-2008

r,

 

Vccaux is used for IO pre-drivers.  And, when a device gets zapped, it may well have been through the Vccaux pins that the zap traveled.

 

It doesn't leave a "went this way" signpost.

 

The zap always takes the shortest path to ground.  Amazing how one always finds out how the path taken, was actually the path of least resistance (literally).

 

One of things about physics that I really love:  consistency.

 

If one tears the device apart (which we often do to check how well the ESD works), one always finds the path -- much like a lightening strike in a forest:  follow the carbon.

 

 

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Scholar
Scholar
6,400 Views
Registered: ‎02-27-2008

r,

 

Yes.  As robust as the FPGA device is (by design, technology, etc.) it is still a CMOS device, which has absolute maximum ratings.  Beyond these ratings, damage and perhaps end of life results.

 

http://www.xilinx.com/support/documentation/data_sheets/ds183_Virtex_7_Data_Sheet.pdf

 

See table 1.

 

In:

 

http://www.xilinx.com/support/documentation/user_guides/ug116.pdf

 

on pages 16 through 21, details of what ""zaps" will be tolerated, and what ones will destroy the device are presented, by technology node and product.

 

Clearly,  as the feature sizes become smaller, the devices are more likely to be damaged by ESD.

 

That is why ESD handling precautions are required while assembling the devices, and ESD clamps and other circuits are required anytime these devices may get handled by people (or machines).

 

Sounds like you now have a completely frapped device,

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Anonymous
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Hi Austin,

 

Thanks for the quick reply.

 

A complete write-off !

 

What's the failure mechanism that involves the Vccaux rail though? I thought that would have nothing to do with the I/Os.

 

Rog.

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Scholar
Scholar
7,945 Views
Registered: ‎02-27-2008

r,

 

Vccaux is used for IO pre-drivers.  And, when a device gets zapped, it may well have been through the Vccaux pins that the zap traveled.

 

It doesn't leave a "went this way" signpost.

 

The zap always takes the shortest path to ground.  Amazing how one always finds out how the path taken, was actually the path of least resistance (literally).

 

One of things about physics that I really love:  consistency.

 

If one tears the device apart (which we often do to check how well the ESD works), one always finds the path -- much like a lightening strike in a forest:  follow the carbon.

 

 

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Anonymous
Not applicable
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Austin,

 

OK, thanks for the information. I understand a lot more now.

 

I'll see if the board can be salvaged with a replacement device next.

 

Regards,

 

Roger.

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Contributor
Contributor
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Registered: ‎12-23-2009

I want to note what the same kind of damage is expected with improper hotplug or Vcco power design.

I think you need to carefuly check the functionality and voltage limits on affected Vcco and damaged IO pins both on your device and the device it mates with.

In my point of view, a random ESD event is less probable than some external connection design problem.

Of course, if that's the only one broken board of 1000's sold over the years, well, ESD is the answer. Otherwise, it is not.

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