We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Visitor kwiatlab
Registered: ‎04-18-2011

Virtex-6 ISERDES differential pin reversed?



I am using a HiTech Global Virtex-6 PCIe board, with a LX365T-P1759-3 chip. I have 16 differential inputs all going in to IBUFDS and then in to ISERDES. All of the 16 ISERDES blocks are the same... but when I hook up a logical zero to all of them, I get all zeroes out.. except for one pin, which gets a 1. When I hook up logical one.. I get all 1's out.. except one zero. The same pin.


I have looked at the pinout.. and I have it set to the differential pair of AV23 and AU22 ... and the positive and negative rails are connected right.... I GUESS I could just swap the p and n inputs.. but that doesn't tell me what the problem is. Any ideas?



0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎09-24-2007

Re: Virtex-6 ISERDES differential pin reversed?

The documents all say you are OK, but the actual board implementation may be a different story.  Did you ring out the traces to the FPGA balls to see if they are correct?

0 Kudos
Scholar drjohnsmith
Registered: ‎07-09-2009

Re: Virtex-6 ISERDES differential pin reversed?



I guess the answer is , it could be a bug.


being practical, it is easy to flip in the code, and it does not add delay to the signal.


<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos