09-21-2015 10:09 AM
For one of our Designs, We use Virtex II. Doee the new Digital Down converter core works with Virtex II designs. I see the Old DDC V1.0 is a drop in modukle for Virtex II series. How do I generate this core, as i could not find the DDC function in the Coregenerator 10.1 version.
I need to implement this ASAP, any guidance is highly appreciated.
09-21-2015 11:06 AM
09-21-2015 02:21 PM
I am using ISE10.1, But in the coregen I donot see DUC or DDC(digital down converter), how can I create DDC with the required decimation and other features and instantiate in the project. I see DDC wi the new version not with the 10.1. But Virtex II is supported only with 10.1 or older.
09-21-2015 09:51 PM
09-22-2015 08:29 AM
I have attached DDC 1.0 core document, which cleary states its compatible with virtex II. IXilinx 10.1 was the last version to support virtex II. But in 10.1 coregen I dont see DDC function.
When I installed 7.1ISE, all the features(Chip Viewer, Architecture Woizard, Floorplanner, Constraint Editor are installed other than coregen 7.1).
ISE12.1 as you mentioned may support DDC 1.0 but the ise12.1 do not support Virtex II. Can I generate DDC1.0 with 12.1 version and compile the project targeting viortex II in ISE10.1, the tool will fail during translate as it will not recognize DDC cores. Please advice.