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Visitor sarithab
Visitor
13,616 Views
Registered: ‎09-26-2013

Virtex5 fpga I/O state during configuration

Hi,

 

We are using Virtex 5 FPGA in our design. The design has few digital outputs which are driven by the FPGA output.

I have observed that, During the FPGA configuration, the FPGA output is being driven to "LOW" state which is operating the external devices.

We have gone through the application notes and connected "HSWAPEN" pin to ground to control the output state of FPGA by enabling the internal pull up resistors.

But even with this  the FPGA output is being driven to low state for about 5mS (tPOR ---Power on reset time).

Please suggest  how to resolve this issue.   

Thanks

Saritha

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7 Replies
Instructor
Instructor
13,609 Views
Registered: ‎08-14-2007

Re: Virtex5 fpga I/O state during configuration

Have you checked that the Vcco for the bank driving these signals low is actually powered during the POR time?  Also check whether the offending pins are "multipurpose" pins which might have a different definition before or during configuration.

-- Gabor
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Xilinx Employee
Xilinx Employee
13,603 Views
Registered: ‎08-01-2012

Re: Virtex5 fpga I/O state during configuration

 If you follow the power-up sequence (VCCINT, VCCAUX, VCCO) then IO will be in HI Z state after  internal Power on Reset(POR) and before HSWAPEN reading. The IO state during configuration depends upon HSWAPEN  input pin status.

 

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Visitor sarithab
Visitor
13,589 Views
Registered: ‎09-26-2013

Re: Virtex5 fpga I/O state during configuration

Thanks  for quick reply.

 

We are not following the power-up sequence in our design. We are providing VCCO(3.3V)  from the  power supply card and VCCINT, VCCAUX are generated on the board taking VCCO(3.3V) as input .

 

I have connected HSWAPEN to "0".

 

Please suggest if there is any documentation regarding the power-up sequence for virtex5 fpga.

 

 

-Saritha

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Xilinx Employee
Xilinx Employee
13,585 Views
Registered: ‎01-03-2008

Re: Virtex5 fpga I/O state during configuration

> Please suggest if there is any documentation regarding the power-up sequence for virtex5 fpga.

 

This is documented in the Virtex-5 data sheet DS202 in the "Power-on Power Supply Requirements" section and it matches the information in a prior post.

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Visitor sarithab
Visitor
13,560 Views
Registered: ‎09-26-2013

Re: Virtex5 fpga I/O state during configuration

I am new to FPGA design.

 

As per the datasheet of virtex 5 Power Supply Ramp Time is specified as 0.20 to 50.0ms. I am not able to figure out the delay time  required  between the power rails while sequencing. 

 

The reason for asking this question is , I am planning to use LM3880 Power Sequencer in my design and these parts are available with different  time delays (refer Table2.TimingDesignator Table  in the below mentioned datasheet ).

 

http://www.ti.com/lit/ds/symlink/lm3880.pdf

 

 

Please  suggest if any power sequence circuit is available for virtex 5.

 

Thanks

  -Saritha

 

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Instructor
Instructor
13,552 Views
Registered: ‎08-14-2007

Re: Virtex5 fpga I/O state during configuration


@mcgett wrote:

> Please suggest if there is any documentation regarding the power-up sequence for virtex5 fpga.

 

This is documented in the Virtex-5 data sheet DS202 in the "Power-on Power Supply Requirements" section and it matches the information in a prior post.


Here's a quote from that section:

 

The power supplies can be turned on in any sequence,
though the specifications shown in Table 5 are for the
recommended power-on sequence of VCCINT, VCCAUX, and
VCCO. The I/O will remain 3-stated through power-on if the
recommended power-on sequence is followed. Xilinx does
not specify the current or I/O behavior for other power-on
sequences.

 

After looking at Table 5 I scratched my head a bit until I realized that the sequence is not listed in that table, but in the statement "... for the recommended power-on sequence of VCCINT, VCCAUX, and VCCO..."

 

Table 5 shows minimum current requirements.  There are no specific timing requirements, and thus it is implied that no damage will occur to the device if this sequence is followed regardless of the delay.  Normally if there are minimum delay requirements, they are specified in terms of a minimum/maximum differential between two supply voltages rather than as a specific delay time.

 

In my experience, the important part is the sequence in which each supply reaches its internal threshold to allow configuration.  Thus to be safe you can just make sure that the delay between supply turn-on is greater than the time each supply takes to ramp up.  I believe the LM3880 should be usable for this, but you need to check the minimum/maximum ramp times of your supplies.

-- Gabor
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Visitor syemets_xil
Visitor
13,394 Views
Registered: ‎02-28-2013

Re: Virtex5 fpga I/O state during configuration

Hi!

Is there dedicated pins in Virtex 5, that holds exact state during all time after power on and before configuration complete.

For example the DONE pin is 0 during configuration and 1 after. Does the pin 0 after power on, but before INIT rises?
Are there some other pin with same function? I do not wish to use DONE for external device control.

The active drive pin is required. Internal or external pullup/pulldown is not suitable.

Thanks.
Sergey.
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