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Newbie ghostong
Registered: ‎04-21-2010

What is the plan of supporting 3.3V peripheral using virtex-6

The V6 has a VCCO maximum at 3.0V. and Vin max = VCCO+0.5V, recommeded VCCO is 2.5V


However, we have lots of 3.3V or 3.0V device (like NAND flash, SDRAM, LCD module.....)


What is the plan of xilinx ?



I have found an answer about how to interact with a 3.3V SPI device if VCCO is 2.5V.

The answer is assume 2.5V signal on clk, cs, mosi (docan be detect by 3.3V SPI since 2.5V is larger than 70% of 3.3V (VIH)

And for the miso (di) , xilinx answer is to ask us to put a 120ohm resistor to ground to reduce the swing from 3.3V to 2.5V.


This doesn't make sense to me.

If all pin need a resistor, it will need lot of PCB space and it will be very hot (2.5V / 120ohm = 50mW) on those resistor.

And this is just uni-direction case.


For bi-direction bus. If the 120ohm resistor is on board. V6 2.5V IO need to overcome this pull down current and maintain a level above 2.3V (70% of 3.3V) would be almost impossible with only 200mV of drop at 20mA of driving current.



Is it possible that we put the VCCO at 2.9V so that nothing is need on board.

For a 3.3V device, it is definitely above VIH.

For 3.3V of VIN, it is still < VCCO + 0.5V. so it would't turn on the ESD device on V6.


But the ringing on VCCO has potential risk of exceed 3.0V with a short duration of time.

This would need Xilinx to judge the robustness of their V6.



Altera stratix-4 (also 40nm process like V6can sustain up to 3.9V which is much better in this case


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Xilinx Employee
Xilinx Employee
Registered: ‎01-03-2008

Re: What is the plan of supporting 3.3V peripheral using virtex-6

See XAPP899 for this information



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