07-09-2009 01:22 PM
This is first time I am using IODELAY element and I got few question hope someone can help me.
1) Do I need to use something like core generator to create IODELAY design with desired attribute? I don't see such option in core generator. Do I just follow template file when instantiating IODELAY?
2) I want to delay clock which is output from a PLL. Can I use IODELAY after PLL?
3) I want to have dynamic control of delay. From the user virtex user guide, it says I need to instantiate IDELAYCTRL primitive, but I am not sure how to connect IODELAY with IDELAYCTRL. Actually I don't even see why IDELAYCTRL is needed for dynamic control.
4) what is the frequency range for IODELAY primitive? I have 125Mhz clock, will that be enough?
07-09-2009 04:54 PM
You can find all the information in "Input/Output Delay Element (IODELAY)" and "IDELAYCTRL Usage and Design Guidelines" sections of the UG190 document.
You can instantiate IDELAY primitive directly
Specify variable delay mode (IDELAY_TYPE = VARIABLE). IDELAYCTRL REFCLK frequency defines the tap resolution.
07-10-2009 07:12 PM
Also see the "IDELAYCTRL_REF" entry in the Virtex-5 datasheet (ds202.pdf).
This can also be a good reference even though it was written originally for V4:
http://www.xilinx.com/support/documentation/application_notes/xapp707.pdf (Advanced ChipSync Applications)