05-23-2011 01:26 AM
05-23-2011 01:48 AM
05-23-2011 02:18 AM
OK, but also i need to know "is the design optimized or not?" and how can i measuer the c=performance
05-23-2011 02:45 AM
the optimizations, done with your design, can be seen in the reports for synthesis, translate and map.
You can controll this by settting tool preferences and constraints in the UCF file.
The easiest way to check the performance is by looking at the static timing analysis report and doing a post-par netlist simulation.
The real hardware may be a little better than that, because the tools work with worst case settings by default.
Measuring the performance is definitely more complicated, since you need some setup that works with your circuit, and indicates wrong behavior that occurs e.g. when you apply a clock freqency > Fmax reported by the static timing analysis.
Wether your design is optimized or not is very hard to prove by measurement. The logical behavior should be the same.
It may be that there is a difference in the power consumption, but for that purpose you need to do some power calculations with the XPower tool on your unoptimized (as far as that is possible at all) and optimized design and then compare these values with your measurements.
Have a nice synthesis
05-24-2011 01:17 AM
thanks for reply
you said "You can controll this by settting tool preferences and constraints in the UCF file." can you inform me ho w i can do that? simply
can you slao explaine the Measuring the performance of design?
wait your reply
05-24-2011 06:52 AM
unfortunately it's not that simple to explain.
Because there is a large number of systhesis options available which have very different effects on your design.
Let's just mention one.
If you have a design with big combinatorical parts and make otherwise no use of BRAMs, then it could be useful to allow BRAMs to be used for implementing combinatorical stuff. This would save many ressources and greatly improve timing.
Or if you have a very complex pipeline that doesn't meet the required timing. Then you could use the register balancing options to let XST move some logic between pipeline stages automatically to find the best timing.
What's good and useful for your design depends on the design itself. You have to see and find out.
Measuring Fmax for a given hardwqare works just the way described in my last posting.
But actually it's a waste of time.
In the end you have to use the static timing analysis value for Fmax to be sure that your design runs on every chip under the allowed environmental settings (Temperature, supply voltage etc.)
For some problem you have to meet a required value (e.g. Fmax or number of calculations), stated in the specifications of the system you are about to design.
If that requirement is fullfiled, your design has enough "performance".
The true question is, how to meet the requirement using less ressources or power. That can save money.
Have a nice synthesis