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Adventurer
Adventurer
8,537 Views
Registered: ‎11-17-2009

how to use DCM in vertex-5 LX50T

i am a bit new user to FPGA, i have a problem in generating 450MHz clock through the use of DCM, i am using  virtex-5 FPGA LX50T.

 

Here is a sample code i am trying all four type of DCM, but still same problem

------------------------------------------------------------------------------------------------------------------------------------------------------------

module checkk(clk,rst,clk_final,CLKIN_IBUFG_OUT,locked);  
input clk;
input rst;
output clk_final;
output CLKIN_IBUFG_OUT;
output locked;
// Instantiate the DCM module
dcmm instance_name (
    .CLKIN_IN(clk),
    .RST_IN(rst),
    .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT),
    .CLKOUT0_OUT(clk_final),
    .LOCKED_OUT(locked)
    );
wire [35:0] ILAControl;
icon i_icon(.CONTROL0(ILAControl));
ila i_ila(.CONTROL(ILAControl), .CLK(clk_final), .TRIG0(clk_final) );

endmodule

----------------------------------------------------------------------------------------------------------------------------------------

 

I am facing a problem  when i assign clk to global clock pin through user constraints, error is there that pin is driving non iobuf pin, when i search that option on xilinx,it says turn off automatic iobuf insertion option, i have done that but still place are route does not complete, althogh no error is displayed, the logs for "place & route" are attached in attached file,some importants warnings are

 

-----------------------------------------------------------------------------------------------------------------------------------------

 WARNING:Par:288 - The signal i_ila_2/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/rd_data<8> has no load.
   PAR will not attempt to route this signal.

WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish
   the rest of the design and leave them as unrouted, The cause of this behavior is either an issue with the placement
   or unroutable placement constraints. To allow you to use FPGA editor to isolate the problems, the following is a list
   of (up to 10) such unroutable connections:
     Unroutable      signal: dcm12_1/CLKOUTDCM0_CLKIN      pin:  dcm12_1/FD2_Q_OUT/CLK
     Unroutable      signal: dcm12_1/CLKOUTDCM0_CLKIN      pin:  dcm12_1/FD1_Q_OUT/CLK
     Unroutable      signal: dcm12_1/CLKOUTDCM0_CLKIN      pin:  dcm12_1/FD3_Q_OUT/CLK
     Unroutable      signal: dcm12_1/CLKOUTDCM0_CLKIN      pin:  dcm12_1/FDS_Q_OUT/CLK

 -----------------------------------------------------------------------------------------------------------------------------------------

 Now i need your help, how to give proper clock input to DCM??  and which type of DCM to use?? i will be very very greatfull if you explain this

specially with some example

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6 Replies
Voyager
Voyager
8,530 Views
Registered: ‎08-30-2007

Re: how to use DCM in vertex-5 LX50T

Where do you create the signal CLKIN_IBUFG_OUT?

 

I don't know what's in your DCMM module, but typically the DCM output

feeds into a BUFG.  The BUFG output drives the global clock and also the

CLKFB input on the DCM.

 

John Providenza

 

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Adventurer
Adventurer
8,509 Views
Registered: ‎11-17-2009

Re: how to use DCM in vertex-5 LX50T

Dear
jprovidenza

 

i have attached the details of dcmm module, it is a DCM to PLL v9.1 formed using ip core insertion and then select clocking and the virtex-5 as shown in this figure

it is basically a 

 

can you please tell me how dcm will work  in this case

 

 

thanks

Uzair

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Adventurer
Adventurer
8,507 Views
Registered: ‎11-17-2009

Re: how to use DCM in vertex-5 LX50T

i have attached the details of dcmm module, it is a DCM to PLL v9.1 formed using ip core insertion and then select clocking and the virtex-5 as shown in this figure

 

 

can you please tell me how dcm will work  in this case

 

 

thanks

Uzair

dcmm_detail.bmp
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Voyager
Voyager
8,492 Views
Registered: ‎08-30-2007

Re: how to use DCM in vertex-5 LX50T

Are you sure the DCM/PLL is causing your problem?

 

Why don't you comment out the module and replace it with a simple BUFG to see if that

changes the problem.

 

John Providenza

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Adventurer
Adventurer
8,458 Views
Registered: ‎11-17-2009

Re: how to use DCM in vertex-5 LX50T

ya i am sure, before connecting DCM projects works fine
0 Kudos
8,121 Views
Registered: ‎06-16-2009

Re: how to use DCM in vertex-5 LX50T

On generating the DCM, if you select the clock source as external, there is no need of adding buffer in the input of the DCM.

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