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Contributor
Contributor
9,774 Views
Registered: ‎03-08-2014

problem in code vhdl when use virtex 5 ml506

i have to interface with ac97 codec by vhdl from i found on this forum, everything was fine i can hear audio signal i want, bit when i want to process this audio signal i meet a problem for example when i want to store signal in left and right channel of input ac97 codec, so i use a module  like this

process(clk)                              -- clk for flipflop is clk for ac97 codec

begin

 if clk='1' and clk'event then

  if ac97_ready='1' then             -- ac97_ready will set '1' each 48Khz has a new samples from thi input

x<=data_in (31 downto 16);    -- data in of left channel of ac97 codec

y<=data_in(15 downto 0);       --  data in of right channel of ac97 codec

end if;

end if;

end process;

Sdata_out<=x&y;                     -- output of ac97 codec

but when i download bit file into the board event when i dont connect input of the codec with my laptop, my earphone still hear some things, some things have sound like "boil water"-noise so i dont understand why it happen ???, i try to fix this but doesnt work

PS: if i just use command x<=data_in(31 downto 16) and remove y<=data_in(15 downto 0) in process then the output i can hear audio signal from left channel ( of couse cant hear about right channel

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Xilinx Employee
Xilinx Employee
9,770 Views
Registered: ‎07-11-2011

Re: problem in code vhdl when use virtex 5 ml506

Hi,

 

What is the frequency of  clk in your process, is this the same extarnal clock that you provide to  AC97?

Can you increase it and check?

I think one/more of the lower bits might be inducing noise you may find it by removing one bit at a time  and check if the bit is somehow effected on your board.

 

Ex:-

y<=data_in(15 downto 1) & '0';

y<=data_in(15 downto 2) & '0'  & data_in(0);

 

 

 

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Historian
Historian
9,752 Views
Registered: ‎02-25-2008

Re: problem in code vhdl when use virtex 5 ml506


@babarian1991 wrote:

i have to interface with ac97 codec by vhdl from i found on this forum, everything was fine i can hear audio signal i want, bit when i want to process this audio signal i meet a problem for example when i want to store signal in left and right channel of input ac97 codec, so i use a module  like this

process(clk)                              -- clk for flipflop is clk for ac97 codec

begin

 if clk='1' and clk'event then

  if ac97_ready='1' then             -- ac97_ready will set '1' each 48Khz has a new samples from thi input

x<=data_in (31 downto 16);    -- data in of left channel of ac97 codec

y<=data_in(15 downto 0);       --  data in of right channel of ac97 codec

end if;

end if;

end process;

Sdata_out<=x&y;                     -- output of ac97 codec

but when i download bit file into the board event when i dont connect input of the codec with my laptop, my earphone still hear some things, some things have sound like "boil water"-noise so i dont understand why it happen ???, i try to fix this but doesnt work

PS: if i just use command x<=data_in(31 downto 16) and remove y<=data_in(15 downto 0) in process then the output i can hear audio signal from left channel ( of couse cant hear about right channel


Did you simulate your design?

----------------------------Yes, I do this for a living.
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