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ajinm
Visitor
Visitor
9,205 Views
Registered: ‎03-23-2015

unexpected token

I am encountering unexpected token: 'ksa'

 

Please help me out. How do I rectify it?

 

module dwt(clock,x0,x1,x2,x3,x4,x5,x6,x7,x8,yh,yl);
input clock;
input [16:0]x0,x1,x2,x3,x4,x5,x6,x7,x8;
output [16:0] yh,yl;
reg [16:0] yh,yl;
reg [16:0]l,h;
//wire [15:0]r9;
reg [16:0]r1,r2,r3,r4,r5,r6,r7,r8,r9,r10;
reg [16:0]r11,r12,r13,r14,r15,r16;
reg [16:0]a1,a2,a3,a4,a5,a6,a7,a8,a9,a10;
reg [16:0]a11,a12,a13,a14,a15,a16,a17,a18,a19,a20;
integer x;
parameter alpha = 16'b1011;
parameter beta = 16'b0011;
parameter gamma = 16'b0111;
parameter delta = 16'b1001;
parameter tau = 16'b0010;
parameter tau1 = 16'b0110;


/*assign r2 = x2;
assign r4 = x4;
assign r6 = x6;*/
always@(posedge clock)
begin
ksa s1(x0,x2,a1,0,0);
a2 = mult(alpha, a1,x);
ksa s2(a2,x1,r1,0,0);
r2 = x2;
//end

//always@(posedge clock)
//begin
ksa s3(x2,x4,a3,0,0);
a4 = mult(a3,alpha,x);
ksa s4(a4,x3,r3,0,0);
r4 = x4;
//end

//always@(posedge clock)
// begin
ksa s5(x4,x6,a5,0,0);
a6 = mult(a5,alpha,x);
ksa s6(a6,x5,r5,0,0);
r6 = x6;
//end

//always@(posedge clock)
//begin
ksa s7(x6,x8,a7,0,0);
a8 = mult(a7,alpha,x);
ksa s8(a8,x7,r7,0,0);
//r8 = x6;
//end

//always@(posedge clock)
//begin
ksa s9(r1,r3,a9,0,0);
a10 = mult(a9,beta,x);
ksa s10(a10,r2,r8,0,0);
r9 = r3;
//end


ksa s11(r3,r5,a11,0,0);
a12 = mult(a11,beta,x);
ksa s12(a12,r4,r10,0,0);
r11 = r5;

ksa s13(r5,r7,a13,0,0);
a14 = mult(a13,beta,x);
ksa s14(a14,r6, r12,0,0);
//assign r11 = r5;

ksa s15(r8,r10,a15,0,0);
a16 = mult(a15,gamma,x);
ksa s16(a16,r9,r13,0,0);
r14 = r10;

ksa s17(r10,r12,a17,0,0);
a18 = mult(a17,gamma,x);
ksa s18(a18,r11,r15,0,0);
h = r15;

ksa s19(r13,r15,a19,0,0);
a20 = mult(a19,delta,x);
ksa s20(a20,r14,r16,0,0);
l = r16;


yh = h*tau;
yl = l*tau1;
end

function mult;
input [3:0] a,b;
input start;
//output [7:0] prod;

reg [7:0] prod;
reg [3:0] b_reg;
reg [3:0] count;

//always@(posedge clock)
begin
b_reg = b;
prod = 0;
count = 4'b0100;
//end
if((a!=0) && (b!=0))
while(count)
begin
mult = {(({4{b_reg[0]}} & a) + prod[7:4]),prod[3:1]};
b_reg = b_reg >> 1;
count = count - 1;
end
end
endfunction
endmodule
module ksa (x, y, sum, cin, cout);
//kogge stone structural model
input [7:0] x, y; //input
output [7:0] sum; //output
input cin; //carry-in
output cout; //carry-out
wire [7:0] G_Z, P_Z, //wires
G_A, P_A,
G_B, P_B,
G_C, P_C;

//level 1
gray_cell level_0A(cin, P_Z[0], G_Z[0], G_A[0]);
black_cell level_1A(G_Z[0], P_Z[1], G_Z[1], P_Z[0], G_A[1], P_A[1]);
black_cell level_2A(G_Z[1], P_Z[2], G_Z[2], P_Z[1], G_A[2], P_A[2]);
black_cell level_3A(G_Z[2], P_Z[3], G_Z[3], P_Z[2], G_A[3], P_A[3]);
black_cell level_4A(G_Z[3], P_Z[4], G_Z[4], P_Z[3], G_A[4], P_A[4]);
black_cell level_5A(G_Z[4], P_Z[5], G_Z[5], P_Z[4], G_A[5], P_A[5]);
black_cell level_6A(G_Z[5], P_Z[6], G_Z[6], P_Z[5], G_A[6], P_A[6]);
black_cell level_7A(G_Z[6], P_Z[7], G_Z[7], P_Z[6], G_A[7], P_A[7]);

//level 2
gray_cell level_1B(cin, P_A[1], G_A[1], G_B[1]);
gray_cell level_2B(G_A[0], P_A[2], G_A[2], G_B[2]);
black_cell level_3B(G_A[1], P_A[3], G_A[3], P_A[1], G_B[3], P_B[3]);
black_cell level_4B(G_A[2], P_A[4], G_A[4], P_A[2], G_B[4], P_B[4]);
black_cell level_5B(G_A[3], P_A[5], G_A[5], P_A[3], G_B[5], P_B[5]);
black_cell level_6B(G_A[4], P_A[6], G_A[6], P_A[4], G_B[6], P_B[6]);
black_cell level_7B(G_A[5], P_A[7], G_A[7], P_A[5], G_B[7], P_B[7]);

//level 3
gray_cell level_3C(cin, P_B[3], G_B[3], G_C[3]);
gray_cell level_4C(G_A[0], P_B[4], G_B[4], G_C[4]);
gray_cell level_5C(G_B[1], P_B[5], G_B[5], G_C[5]);
gray_cell level_6C(G_B[2], P_B[6], G_B[6], G_C[6]);
black_cell level_7C(G_B[3], P_B[7], G_B[7], P_B[3], G_C[7], P_C[7]);

//level 4
gray_cell level_7D(cin, P_C[7], G_C[7], cout);

//xor with and
and_xor level_Z0(x[0], y[0], P_Z[0], G_Z[0]);
and_xor level_Z1(x[1], y[1], P_Z[1], G_Z[1]);
and_xor level_Z2(x[2], y[2], P_Z[2], G_Z[2]);
and_xor level_Z3(x[3], y[3], P_Z[3], G_Z[3]);
and_xor level_Z4(x[4], y[4], P_Z[4], G_Z[4]);
and_xor level_Z5(x[5], y[5], P_Z[5], G_Z[5]);
and_xor level_Z6(x[6], y[6], P_Z[6], G_Z[6]);
and_xor level_Z7(x[7], y[7], P_Z[7], G_Z[7]);

//outputs
xor(sum[0], cin, P_Z[0]);
xor(sum[1], G_A[0], P_Z[1]);
xor(sum[2], G_B[1], P_Z[2]);
xor(sum[3], G_B[2], P_Z[3]);
xor(sum[4], G_C[3], P_Z[4]);
xor(sum[5], G_C[4], P_Z[5]);
xor(sum[6], G_C[5], P_Z[6]);
xor(sum[7], G_C[6], P_Z[7]);

endmodule

//other modules
module black_cell(Gkj, Pik, Gik, Pkj, G, P);
//black cell
input Gkj, Pik, Gik, Pkj;
output G, P;
wire Y;

and(Y, Gkj, Pik);
or(G, Gik, Y);
and(P, Pkj, Pik);

endmodule

module gray_cell(Gkj, Pik, Gik, G);
//gray cell
input Gkj, Pik, Gik;
output G;
wire Y;

and(Y, Gkj, Pik);
or(G, Y, Gik);

endmodule

module and_xor(a, b, p, g);
//very first inputs - and/xor
input a, b;
output p, g;

xor(p, a, b);
and(g, a, b);

endmodule

 

ksa.png

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3 Replies
pratham
Scholar
Scholar
9,192 Views
Registered: ‎06-05-2013

Hello,

What is KSA here?
-Pratham

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ajinm
Visitor
Visitor
9,182 Views
Registered: ‎03-23-2015

kogge stone adder

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gszakacs
Professor
Professor
9,087 Views
Registered: ‎08-14-2007

It looks like you took some code that was in a process and then tried to make a continuous assignment from it.  In verilog, a continuous assignment needs to start with the keyword "assign".

 

For example in a process you can write:

 

reg a, c;

always @*

  begin

    a = b;

    c = d;

  end

 

But writing the equivalent outside a process needs to look like:

 

wire a, c;

assign a = b;

assign c = d;

 

In addition, unless you are using SystemVerilog, a and c need to be declared differently for these two approaches.  To drive a dn c within a process, they must be declared as reg, but outside a process they must be wire.  In SystemVerilog they could be declared as logic for both cases.

-- Gabor
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