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Visitor yuxdntu
Visitor
5,900 Views
Registered: ‎04-08-2010

vertiex 5 reset handling

Hi, all

 

I have a question on how to handle the reset signal in virtex 5. I use synchronous reset signal which is used to reset entire design. The timing for the reset signal is hard to meet since the fan out is big. If I reduce fan out limit in synplify pro. I get a lot of replicated lines for the rest. which take many logic. There should be better solution. anybody can help on that? 

 

regards

xiaodong yu

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7 Replies
Historian
Historian
5,887 Views
Registered: ‎02-25-2008

Re: vertiex 5 reset handling


yuxdntu wrote:

Hi, all

 

I have a question on how to handle the reset signal in virtex 5. I use synchronous reset signal which is used to reset entire design. The timing for the reset signal is hard to meet since the fan out is big. If I reduce fan out limit in synplify pro. I get a lot of replicated lines for the rest. which take many logic. There should be better solution. anybody can help on that? 

 

regards

xiaodong yu


The following might sound flip, but it's not meant to be: Reset only those registers which require a reset. 

----------------------------Yes, I do this for a living.
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Observer paubert
Observer
5,880 Views
Registered: ‎03-25-2009

Re: vertiex 5 reset handling

From the documentation (and a quick look in FPGA editor), the global buffers are not limited to clock inputs on V5.

 

If you have free global buffers (likely since there are 32) and free global clock lines (10 per region),  inserting a global buffer on the reset distribution might help. It adds some latency but at least propagation delay is quite uniform across the chip.

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Visitor flitch@home
Visitor
5,840 Views
Registered: ‎03-09-2010

Re: vertex 5 reset handling

Hi,

 

The final step during configuration is to clear all registers to 0. This usually takes care of the power up reset state.

 

We however, also provide a post-configuration reset (using an external device) which triggered when DONE goes low to high.

 

If your reset is genuinely synchronous then you can simply distribute it around the device and then retime it in each major block. This will dramatically reduce the loading and speed it up. You should of course double retime at the top level, prior to distribution to avoid metastability.

 

Finally, do you really need a synchronous reset? Provided the device recovers cleanly after reset (no problems due to metastability) then why not define a multi-cycle path or use an asynchronous reset instead?

 

Hope this helps.

 

Best wishes

Flitch

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Visitor yuxdntu
Visitor
5,831 Views
Registered: ‎04-08-2010

Re: vertex 5 reset handling

Hi, all

 

thank you very much for your help.   the global buffer can be used on the reset signal. It can drive 3000 fan out with 2.xx ns delay. not bad. but I can not see obvious resource reduction after using global buffer. So I go back to orignal design.

 

The reset pin is controlled by MCU. it will reset FPGA from time  to time. As far as asynchronous reset,  I don't know how the asynchronous reset work with clock. there is potential meta stability. it is just my concern.  Retime the reset is a good idea. but you can not reset the chip with 1 clock. reset

 

Anyway thank you very much for you help.

 

Regards

xiaodong yu  

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Observer paubert
Observer
5,810 Views
Registered: ‎03-25-2009

Re: vertex 5 reset handling


yuxdntu wrote:

Hi, all

 

thank you very much for your help.   the global buffer can be used on the reset signal. It can drive 3000 fan out with 2.xx ns delay. not bad. but I can not see obvious resource reduction after using global buffer. So I go back to orignal design.

 

The reset pin is controlled by MCU. it will reset FPGA from time  to time. As far as asynchronous reset,  I don't know how the asynchronous reset work with clock. there is potential meta stability. it is just my concern.  Retime the reset is a good idea. but you can not reset the chip with 1 clock. reset

 

Anyway thank you very much for you help.

 

Regards

xiaodong yu  


You won't have any visible resource reductions in the synthesis/mapping/par results since inserting a global buffer will not affect the amount of logic resources used and register duplication to limit fanout is hard to trigger on Virtex-5 (can't remember the limit right now, but much larger than for older families).

 

What it will reduce is the amount of short and medium range routing resources used to distribute the signal, freeing them for other uses and possibly helping routing in congested areas. In Spartan-3 the global buffers can only reach clock signals and I'd sometimes wish I could use them for other purposes since in some designs I end up with one or two signals with a large fanout spread all over the chip (this typically ends up with the FF producing the signal being replicated).

 

I suspect that it is not uncommon, otherwise Xilinx would not have added the capability of driving non-clock pins from global buffers in V4/V5/V6/S6. However, while the synthesis tools will typically automatically insert global buffers on clock signals, you have (as far as I know) to instantiate them explicitly for the other cases. Actually I prefer it this way, this means that I stay in control (I hate tools that try to outsmart me). 

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Visitor yuxdntu
Visitor
5,808 Views
Registered: ‎04-08-2010

Re: vertex 5 reset handling

Just remember that long long ago I use "low skew" constraint for a global siganal such as reset. but now it seems not used any more.

 

In fact if use replication of reset signals, it will be some replicated registers. the number of them depends on the total fan out and the settings on fan out limit.  Replication registers are around hundreds in my case. So the reduction of register is not obvious.  The routings of a signal also need slices. Maybe replication of routing traces are not significate too.

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Adventurer
Adventurer
5,793 Views
Registered: ‎10-13-2007

Re: vertiex 5 reset handling

See the PLD blog in these forums. There is one post about why global resets are a bad idea. The article seems to make a lot of sense.

 

CTW

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