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Registered: ‎11-24-2010

virtex-6 oserdes

Hi everyone,


I implemented a 8-bits oserdes in my system. I use a trig signal to control the output timing of the serdes.

As the trig signal was enabled, it will read the FIFO and sent readed data to input of oserdes. I use the chipscope to observe the data output timing of FIFO and it  was fixed evey run but the serial data will shift.


The difference could be found from 1.PNG and 2.PNG. The parallel loaded data was fixed but the serial data will shift.


The device is XC6VLX130T-1C. The CLK of oserdes is 74.375 MHz and CLKDIV is 595 MHz souring from MMCM at the same clock region.


The output latency should be a fixed value, but it seems not, could anyone help me to reslove it ?







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