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Visitor gongjian1990
Visitor
4,413 Views
Registered: ‎03-14-2012

wr_data_count,full signal goes wrong when i use asynchronous FIFO with peeking

Hello,

I use FIFO generator generated a FIFO. The FIFO is an asynchronous one. I chose "First word, first through", so the FIFO is with peeking. The FIFO's width is 72bit, and its depth is 1024(it can store 1023 data accordding to ug175).

however, when i simulate it, there is something strange:

figure 1 on the attachment shows how the FIFO act when inserting data into it. But in the cycle din = 15 and din = 16, the wr_data_count isn't increased. So does the cycle when din = 17 and 18.

figure 2 shows when all the 1023 data are inserted into the FIFO, the wr_data_count is finally 1021, and full, almost_full are not assertted. 

this is strange, when i sroted 1023 data, the full and almost_full should be 1, and wr_data_count should be 1023.

att.png
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2 Replies
Teacher eteam00
Teacher
4,406 Views
Registered: ‎07-21-2009

FIFO simulation models

This may be helpful to you (from PG057, FIFO Generator Product Guide):

 

Note: If independent clocks or common clocks with built-in FIFO is selected, the user must use the structural model, as the behavioral model does not support the built-in FIFO configurations.


Structural Models

 

The structural models are designed to provide a more accurate model of FIFO behavior at the cost of simulation time. These models will provide a closer approximation of cycle accuracy across clock domains for asynchronous FIFOs. No asynchronous FIFO model can be 100% cycle accurate as physical relationships between the clock domains, including temperature, process, and frequency relationships, affect the domain crossing indeterminately.

 

-- Bob Elkind

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Visitor gongjian1990
Visitor
4,395 Views
Registered: ‎03-14-2012

Re: FIFO simulation models

Thank you very much.

I finally find it in UG175. It says the counter is not accurate when the counter's value is small. 

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